XIO2000AI datasheet(51/159 Pages) TAOS

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Feature/Protocol Descriptions

April 2007 Revised October 2008

SCPS155C

Data

Address

CLK

FRAME

LOCK

IRDY

TRDY

DEVSEL

Figure 3−12. Continuing A Locked Sequence

Because PCI Express does not have a unique locked-memory write request packet, all PCI Express memory

write requests that are received while the bridge is locked are considered part of the locked sequence and

are transmitted to PCI as locked-memory write transactions. In addition, all traffic mapped to VC1 is allowed

to pass.

The bridge terminates the locked sequence when an unlock message is received from PCI Express and all

previous locked transactions have been completed.

CLK

FRAME

LOCK

IRDY

Figure 3−13. Terminating A Locked Sequence

In the erroneous case that a normal downstream memory read request is received during a locked sequence,

the bridge responds with an unsupported request completion status. Please note that this condition must

never occur, because the PCI Express specification requires the root complex to block normal memory read

requests at the source. All locked sequences that end successfully or with an error condition must be

immediately followed by an unlock message. This unlock message is required to return the bridge to a known

unlocked state.

3.10 Two-Wire Serial-Bus Interface

The bridge provides a two-wire serial-bus interface to load subsystem identification information and specific

two of the GPIO terminals (4 and 5). If the serial bus interface is enabled, then the GPIO4 and GPIO5 terminals

are disabled. If the serial bus interface is disabled, then the GPIO terminals operate as described in

Section 3.13.

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