XIO2000AI datasheet(38/159 Pages) TAOS

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Feature/Protocol Descriptions

April 2007 Revised October 2008

SCPS155C

If the REFCLK_SEL (A16) input is connected to VSS, then a differential, 100-MHz common clock reference

is expected by the bridge. If the A16 terminal is connected to VDD_33, then a single-ended, 125-MHz clock

reference is expected by the bridge.

When the single-ended, 125-MHz clock reference option is enabled, the single-ended clock signal is

connected to the REFCLK+ (C17) terminal. The REFCLK− (C16) terminal is connected to one side of an

external capacitor with the other side of the capacitor connected to VSS.

When using a single-ended reference clock, care must be taken to ensure interoperability from a system jitter

standpoint. The PCI Express Base Specification does not ensure interoperability when using a differential

reference clock commonly used in PC applications along with a single-ended clock in a noncommon clock

architecture. System jitter budgets will have to be verified to ensure interoperability. See the PCI Express Jitter

and BER White Paper from the PCI-SIG.

3.3.2 Beacon

The bridge supports the PCI Express in-band beacon feature. Beacon is driven on the upstream PCI Express

link by the bridge to request the reapplication of main power when in the L2 link state. To enable the beacon

feature, bit 10 (BEACON_ENABLE) in the general control register at offset D4h is asserted. See Section 4.65,

General Control Register, for details.

If the bridge is in the L2 link state and beacon is enabled, when a secondary PCI bus device asserts PME,

then the bridge outputs the beacon signal on the upstream PCI Express link. The beacon signal frequency

is approximately 500 kHz

± 50% with a differential peak-to-peak amplitude of 500 mV and no de-emphasis.

Once the beacon is activated, the bridge continues to send the beacon signal until main power is restored as

indicated by PERST going inactive. At this time, the beacon signal is deactivated.

3.3.3 Wake

The bridge supports the PCI Express sideband WAKE feature. WAKE is an active low signal driven by the

bridge to request the reapplication of main power when in the L2 link state. Since WAKE is an open-collector

output, a system-side pullup resistor is required to prevent the signal from floating.

When the bridge is in the L2 link state and PME is received from a device on the secondary PCI bus, the WAKE

signal is asserted low as a wakeup mechanism. Once WAKE is asserted, the bridge drives the signal low until

main power is restored as indicated by PERST going inactive. At this time, WAKE is deasserted.

3.3.4 Initial Flow Control Credits

The bridge flow control credits are initialized using the rules defined in the PCI Express Base Specification.

Table 3−2 identifies the initial flow control credit advertisement for the bridge. The initial advertisement is

exactly the same when a second virtual channel (VC) is enabled.

Table 3−2. Initial Flow Control Credit Advertisements

CREDIT TYPE

INITIAL ADVERTISEMENT

Posted request headers (PH)

Posted request data (PD)

128

Nonposted header (NPH)

Nonposted data (NPD)

Completion header (CPLH)

0 (infinite)

Completion data (CPLD)

0 (infinite)

3.3.5 PCI Express Message Transactions

PCI Express messages are both initiated and received by the bridge. Table 3−3 outlines message support

within the bridge.

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