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XIO2000AI 数据表(PDF) 96 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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XIO2000AI 数据表(HTML) 96 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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96 / 159 page  Classic PCI Configuration Space 86 April 2007 Revised October 2008 SCPS155C 4.66 Clock Control Register This register enables and disables the PCI clock outputs (CLKOUT). See Table 4−40 for a complete description of the register contents. PCI register offset: D8h Register type: Read-only, Read/Write Default value: 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 4−40. Clock Control Register Description BIT FIELD NAME ACCESS DESCRIPTION 7 RSVD R Reserved. Returns 0b when read. 6† CLOCK6_DISABLE RW Clock output 6 disable. This bit disables secondary CLKOUT6. 0 = Clock enabled (default) 1 = Clock disabled 5† CLOCK5_DISABLE RW Clock output 5 disable. This bit disables secondary CLKOUT5. 0 = Clock enabled (default) 1 = Clock disabled 4† CLOCK4_DISABLE RW Clock output 4 disable. This bit disables secondary CLKOUT4. 0 = Clock enabled (default) 1 = Clock disabled 3† CLOCK3_DISABLE RW Clock output 3 disable. This bit disables secondary CLKOUT3. 0 = Clock enabled (default) 1 = Clock disabled 2† CLOCK2_DISABLE RW Clock output 2 disable. This bit disables secondary CLKOUT2. 0 = Clock enabled (default) 1 = Clock disabled 1† CLOCK1_DISABLE RW Clock output 1 disable. This bit disables secondary CLKOUT1. 0 = Clock enabled (default) 1 = Clock disabled 0† CLOCK0_DISABLE RW Clock output 0 disable. This bit disables secondary CLKOUT0. 0 = Clock enabled (default) 1 = Clock disabled † These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset. |
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