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XIO2000AI 数据表(PDF) 43 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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XIO2000AI 数据表(HTML) 43 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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43 / 159 page  Feature/Protocol Descriptions 33 April 2007 Revised October 2008 SCPS155C 3.5.1 PCI Port Arbitration The internal PCI port arbitration logic supports up to six external PCI bus devices plus the bridge. Three options exist when configuring the bridge arbiter for these seven bus devices: classic PCI arbiter, 128-phase, WRR time-based arbiter, and 128-phase, WRR aggressive time-based arbiter. 3.5.1.1 Classic PCI Arbiter The classic PCI arbiter is configured through the classic PCI configuration space at offset DCh. Table 3−5 identifies and describes the registers associated with classic PCI arbitration mode. Table 3−5. Classic PCI Arbiter Registers PCI OFFSET REGISTER NAME DESCRIPTION Classic PCI configuration register DCh Arbiter control (see Section 4.69) Contains a two-tier priority scheme for the bridge and six PCI bus devices. The bridge defaults to the high priority tier. The six PCI bus devices default to the low priority tier. A bus parking control bit (bit 7, PARK) is provided. Classic PCI configuration register DDh Arbiter request mask (see Section 4.70) Six mask bits provide individual control to block each PCI Bus REQ input. Bit 7 (ARB_TIMEOUT) in the arbiter request mask register enables generating timeout status if a PCI device does not respond within 16 PCI bus clocks. Bit 6 (AUTO_MASK) in the arbiter request mask register automatically masks a PCI bus REQ if the device does not respond after GNT is issued. The AUTO_MASK bit is cleared to disable any automatically generated mask. Classic PCI configuration register DEh Arbiter time-out status (see Section 4.71) When bit 7 (ARB_TIMEOUT) in the arbiter request mask register (see Section 4.70) is asserted, timeout status for each PCI bus device is reported in this register. 3.5.1.2 128-Phase, WRR Time-Based Arbiter The 128-phase, WRR time-based arbiter is configured through the PCI express VC extended configuration space at offset 150h and the device control memory window register map. The 128-phase, WRR time-based arbiter periodically asserts GNT to a PCI master device based on entries within a port arbitration table. There are actually two port arbitration tables within the bridge. The first table is accessed through the PCI Express VC extended configuration register space using configuration read/write transactions. The second table is internal and is used by the PCI bus arbiter to make GNT decisions. A configuration register load function exists to transfer the contents of the configuration register table to the internal table. The port arbitration table uses a 4-bit field to identify the secondary bus master that receives GNT during each phase of the time-based WRR arbitration. For the arbiter to recognize a bus master REQ and to generate GNT, software must allocate at least three consecutive phases to the same port number. Table 3−6 defines the mapping relationship of the PCI bus devices to a port number in the port arbitration table. Table 3−6. Port Number to PCI Bus Device Mapping PORT NUMBER GNT PCI DEVICE 0000b Internal GNT for PCI master state machine Internal REQ from PCI master state machine 0001b External GNT0 External REQ0 0010b External GNT1 External REQ1 0011b External GNT2 External REQ2 0100b External GNT3 External REQ3 0101b External GNT4 External REQ4 0110b External GNT5 External REQ5 0111b−1111b Reserved − |
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