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XIO2000AI 数据表(PDF) 28 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS

部件名 XIO2000AI
功能描述  PCI Express to PCI Bus Translation Bridge
PDF  159 Pages
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制造商  TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]
网页  http://www.taosinc.com
标志 TAOS - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS

XIO2000AI 数据表(HTML) 28 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS

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Introduction
18
April 2007 Revised October 2008
SCPS155C
Table 2−8. PCI Express Terminals
SIGNAL
GZZ/
ZZZ
BALL #
ZHC
BALL #
ZHH
BALL #
I/O
TYPE
CELL
TYPE
CLAMP
RAIL
EXTERNAL
PARTS
DESCRIPTION
PERST
J17
H14
H12
I
LV
CMOS
VDD_33_
COMBIO
−
PCI Express reset input. The PERST
signal identifies when the system power is
stable and generates an internal power on
reset.
Note: The PERST input buffer has
hysteresis.
REF0_PCIE
REF1_PCIE
L16
L17
K14
J13
J14
J13
I/O
BIAS
−
External
resistor
External reference resistor + and −
terminals for setting TX driver current. An
external resistor is connected between
terminals L16 and L17.
RXP
RXN
E17
E16
E13
E14
E14
E13
DI
HS
DIFF IN
VSS
−
High-speed receive pair. RXP and RXN
comprise the differential receive pair for the
single PCI Express lane supported.
TXP
TXN
H17
H16
G14
G13
G14
G13
DO
HS
DIFF
OUT
VDD_15
Series
capacitors
High-speed transmit pair. TXP and TXN
comprise the differential transmit pair for
the single PCI Express lane supported.
WAKE
M16
L14
K14
O
LV
CMOS
VDD_33_
COMBIO
−
Wake is an active low signal that is driven
low to reactivate the PCI Express link
hierarchy’s main power rails and reference
clocks.
Note: Since WAKE is an open-drain output
buffer, a system side pullup resistor is
required.



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