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XIO2000AI 数据表(PDF) 31 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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XIO2000AI 数据表(HTML) 31 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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31 / 159 page  Introduction 21 April 2007 Revised October 2008 SCPS155C Table 2−10. PCI System Terminals (Continued) SIGNAL GZZ/ZZZ BALL # ZHC BALL # ZHH BALL # I/O TYPE CELL TYPE CLAMP RAIL EXTERNAL PARTS DESCRIPTION PAR E02 D03 D02 I/O PCI Bus VCCP − PCI bus parity PERR F03 C01 D03 I/O PCI Bus VCCP Pullup resistor per PCI spec PCI parity error PME M15 M14 L12 I LV CMOS VDD_33_ COMBIO Pullup resistor per PCI spec PCI power management event. This terminal may be used to detect PME events from a PCI device on the secondary bus. Note: The PME input buffer has hysteresis. REQ5 REQ4 REQ3 REQ2 REQ1 REQ0 B13 B12 B11 C10 C09 B08 B12 B11 C09 B09 B08 B07 A12 A11 A10 C09 A08 B07 I PCI Bus VCCP If unused, a weak pullup resistor per PCI spec PCI request inputs. These signals are used for arbitration on the secondary PCI bus when an external arbiter is not used. REQ0 is used as the GNT for the bridge when an external arbiter is used. PRST U03 P01 P01 O PCI Bus VCCP − PCI reset. This terminal is an output to the secondary PCI bus. SERR E01 E03 D01 I/O PCI Bus VCCP Pullup resistor per PCI spec PCI system error STOP F02 D02 E03 I/O PCI Bus VCCP Pullup resistor per PCI spec PCI stop TRDY G03 F03 E01 I/O PCI Bus VCCP Pullup resistor per PCI spec PCI target ready Table 2−11. Reserved Terminals SIGNAL GZZ/ZZZ BALL # ZHC BALL # ZHH BALL # I/O TYPE DESCRIPTION RSVD N15, N16, P16, R08, T08, T10, T11, T12, T14, T15, T17, U09, U11, U12, U13, U14, U15, U16 K12, L07, L12, M10, M11, M13, N06, N08, N09, N10, N11, P05, P06, P08, P09, P10, P13, P14 L07, L10, L14, M06, M12, M13, N06, N08, N09, N10, N11, P06, P08, P09, P10, P11, P12, P14 O Reserved, do not connect to external signals. RSVD R16 N12 N14 I Must be connected to VDD_33. RSVD D16, D17, P17, R09, T09, U10 D12, D14, M07, N07, N14, P07 D13, D14, M14, P07, M07, N07 I Must be connected to VSS. |
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