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XIO2000AI 数据表(PDF) 126 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS

部件名 XIO2000AI
功能描述  PCI Express to PCI Bus Translation Bridge
PDF  159 Pages
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制造商  TAOS [TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS]
网页  http://www.taosinc.com
标志 TAOS - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS

XIO2000AI 数据表(HTML) 126 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS

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PCI Express Extended Configuration Space
116
April 2007 Revised October 2008
SCPS155C
5.26 VC Resource Status Register (VC1)
The VC resource status register allows software to monitor the status of the port arbitration table for this VC.
See Table 5−22 for a complete description of the register contents.
PCI Express extended register offset:
176h
Register type:
Read-only
Default value:
0000h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5−22. VC Resource Status Register (VC1) Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15:2
RSVD
R
Reserved. Returns 00 0000 0000 0000b when read.
1
VC_PENDING
RU
VC negotiation pending. This bit is asserted when VC negotiation is in progress following a
request by software to enable the second VC.
0
PORT_TABLE
_STATUS
RU
Port arbitration table status. This bit is automatically set by hardware when any modification is
made to the port arbitration table entries for this VC within the extended configuration space.
This bit is cleared by hardware after software has requested a port arbitration table refresh and
the refresh has been completed.
5.27 VC Arbitration Table
The VC arbitration table is provided to allow software to define round-robin weighting for traffic targeting the
PCI Express port. The table is divided into 32 phases. See Table 5−24 for a complete description of the register
contents.
PCI Express extended register offset:
180h – 18Ch
Register type:
Read-only, Read/Write
Default value:
0000 0000h
Table 5−23. VC Arbitration Table
REGISTER FORMAT
OFFSET
Phase 7
Phase 6
Phase 5
Phase 4
Phase 3
Phase 2
Phase 1
Phase 0
180h
Phase 15
Phase 14
Phase 13
Phase 12
Phase 11
Phase 10
Phase 9
Phase 8
184h
Phase 23
Phase 22
Phase 21
Phase 20
Phase 19
Phase 18
Phase 17
Phase 16
188h
Phase 31
Phase 30
Phase 29
Phase 28
Phase 27
Phase 26
Phase 25
Phase 24
18Ch
Each phase consists of a four-bit field as indicated below.
BIT NUMBER
3
2
1
0
RESET STATE
0
0
0
0
Table 5−24. VC Arbitration Table Entry Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
3
RSVD
R
Reserved. Returns 0b when read.
2:0
VC_ARB_ID
RW
Virtual channel ID. This 3-bit field is used by software to identify the VC ID that must be allocated
this slot of arbitration bandwidth depending upon the VC arbitration scheme enabled. The default
value for this field is 000b.



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