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数据搜索系统，热门电子元器件搜索 |
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XIO2000AI 数据表(PDF) 133 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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XIO2000AI 数据表(HTML) 133 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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133 / 159 page  Memory-Mapped TI Proprietary Register Space 123 April 2007 Revised October 2008 SCPS155C 6.11 Upstream Isochronous Window 2 Control Register The upstream isochronous window 2 control register allows software to identify the TC associated with upstream transactions targeting memory addresses in the range defined by the window. See Table 6−6 for a complete description of the register contents. Device control memory window register offset: 20h Register type: Read-only, Read/Write Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 6−6. Upstream Isochronous Window 2 Control Register Description BIT FIELD NAME ACCESS DESCRIPTION 15:4 RSVD R Reserved. Returns 000h when read. 3:1 TC_ID RW Traffic class ID. ID of the traffic class that upstream transactions targeting the range defined by the associated window must be mapped to. The default value for this field is 000b. 0 ISOC_WINDOW_EN RW Isochronous window enable. 0 = Address window does not impact upstream traffic (default) 1 = Upstream transactions targeting addresses within the range of this window are applied to the appropriate TC 6.12 Upstream Isochronous Window 2 Base Address Register The upstream isochronous window 2 base address register allows software to configure the base address for this upstream isochronous window. The entire 32-bit field is read/write and acts as scratchpad space if the window is disabled. Device control memory window register offset: 24h Register type: Read/Write Default value: 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6.13 Upstream Isochronous Window 2 Limit Register The upstream isochronous window 2 limit register allows software to configure the upper address bound for this upstream isochronous window. The entire 32-bit field is read/write and acts as scratchpad space if the window is disabled. Device control memory window register offset: 28h Register type: Read/Write Default value: 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
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