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XIO2000AI 数据表(PDF) 149 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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XIO2000AI 数据表(HTML) 149 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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149 / 159 page  Electrical Characteristics 139 April 2007 Revised October 2008 SCPS155C 7.6 PCI Express Differential Reference Clock Input Ranges PARAMETER TERMINALS MIN NOM MAX UNITS COMMENTS fIN-DIFF Differential input frequency REFCLK+ REFCLK− 100 MHz The input frequency is 100 MHz + 300 ppm and − 2800 ppm including SSC-dictated variations. fIN-SE Single-ended input frequency REFCLK+ 125 MHz The input frequency is 125 MHz ± 300 ppm. VRX-DIFFp-p Differential input peak-to-peak voltage REFCLK+ REFCLK− 0.175 1.200 V VRX-DIFFp-p = 2*|VREFCLK+ − VREFCLK−| VIH-SE REFCLK+ 0.7 VDDA_33 VDDA_33 V Single-ended, reference clock mode high-level input voltage VIL-SE REFCLK+ 0 0.3 VDDA_33 V Single-ended, reference clock mode low-level input voltage VRX-CM-ACp AC peak common mode input voltage REFCLK+ REFCLK− 140 mV VRX-CM-ACp =RMS(|VREFCLK++VREFCLK−|/2 – VRX-CM-DC) VRX-CM-DC=DC(avg)of|VREFCLK++VREFCLK−|/2 Duty cycle REFCLK+ REFCLK− 40% 60% Differential and single-ended waveform input duty cycle ZRX-DIFF-DC DC differential input impedance REFCLK+ REFCLK− 20 k Ω REFCLK+/− dc differential mode impedance ZRX-DC DC input impedance REFCLK+ REFCLK− 20 k Ω REFCLK+ dc single-ended mode impedance NOTE 17: The XIO2000A is compliant with the defined system jitter models for a PCI-Express reference clock and associated TX/RX link. These system jitter models are described in the PCI-Express Jitter Modeling, Revision 1.0RD document. Any usage of the XIO2000A in a system configuration that does not conform to the defined system jitter models requires the system designer to validate the system jitter budgets. |
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