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MFRC522 数据表(PDF) 23 Page - NXP Semiconductors

部件名 MFRC522
功能描述  Contactless reader IC
PDF  96 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

MFRC522 数据表(HTML) 23 Page - NXP Semiconductors

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MFRC522_33
© NXP B.V. 2009. All rights reserved.
Product data sheet
PUBLIC
Rev. 3 — 26 October 2009
112133
23 of 96
NXP Semiconductors
MFRC522
Contactless reader IC
8.2 Analog interface and contactless UART
8.2.1 General
The integrated contactless UART supports the external host online with framing and error
checking of the protocol requirements up to 848 kBd. An external circuit can be connected
to the communication interface pins MFIN and MFOUT to modulate and demodulate the
data.
The contactless UART handles the protocol requirements for the communication protocols
in cooperation with the host. Protocol handling generates bit and byte-oriented framing. In
addition, it handles error detection such as parity and CRC, based on the various
supported contactless communication protocols.
Remark: The size and tuning of the antenna and the power supply voltage have an
important impact on the achievable operating distance.
8.2.2 TX p-driver
The signal on pins TX1 and TX2 is the 13.56 MHz energy carrier modulated by an
envelope signal. It can be used to drive an antenna directly using a few passive
components for matching and filtering; see Section 15 on page 78. The signal on pins
TX1 and TX2 can be configured using the TxControlReg register; see Section 9.3.2.5 on
page 48.
The modulation index can be set by adjusting the impedance of the drivers. The
impedance of the p-driver can be configured using registers CWGsPReg and
ModGsPReg. The impedance of the n-driver can be configured using the GsNReg
register. The modulation index also depends on the antenna design and tuning.
The TxModeReg and TxSelReg registers control the data rate and framing during
transmission and the antenna driver setting to support the different requirements at the
different modes and transfer speeds.
[1]
X = Do not care.
Table 15.
Register and bit settings controlling the signal on pin TX1
Bit
Tx1RFEn
Bit
Force
100ASK
Bit
InvTx1RFOn
Bit
InvTx1RFOff
Envelope
Pin
TX1
GSPMos
GSNMos
Remarks
0X[1]
X[1]
X[1]
X[1]
X[1]
X[1]
X[1]
not specified if RF is
switched off
10
0
X[1]
0
RF
pMod
nMod
100 % ASK: pin TX1
pulled to logic 0,
independent of the
InvTx1RFOff bit
1
RF
pCW
nCW
01
X[1]
0
RF
pMod
nMod
1
RF
pCW
nCW
11
X[1]
0
0
pMod
nMod
1
RF_n
pCW
nCW



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