MFRC522 datasheet(38/96 Pages) NXP

38 / 96 page

MFRC522_33

Product data sheet

PUBLIC

Rev. 3 — 26 October 2009

112133

38 of 96

NXP Semiconductors

MFRC522

Contactless reader IC

9.3.1.6

DivIrqReg register

Interrupt request bits.

Table 30.

ComIrqReg register bit descriptions

All bits in the ComIrqReg register are cleared by software.

Bit Symbol

Value Description

Set1

indicates that the marked bits in the ComIrqReg register are set

indicates that the marked bits in the ComIrqReg register are cleared

TxIRq

set immediately after the last bit of the transmitted data was sent out

RxIRq

receiver has detected the end of a valid data stream

if the RxModeReg register’s RxNoErr bit is set to logic 1, the RxIRq bit is

only set to logic 1 when data bytes are available in the FIFO

IdleIRq

If a command terminates, for example, when the CommandReg changes

its value from any command to the Idle command (see Table 149 on

page 67)

if an unknown command is started, the CommandReg register

Command[3:0] value changes to the idle state and the IdleIRq bit is set

The microcontroller starting the Idle command does not set the IdleIRq

bit

HiAlertIRq

the Status1Reg register’s HiAlert bit is set

in opposition to the HiAlert bit, the HiAlertIRq bit stores this event and

can only be reset as indicated by the Set1 bit in this register

LoAlertIRq 1

Status1Reg register’s LoAlert bit is set

in opposition to the LoAlert bit, the LoAlertIRq bit stores this event and

can only be reset as indicated by the Set1 bit in this register

ErrIRq

any error bit in the ErrorReg register is set

TimerIRq

the timer decrements the timer value in register TCounterValReg to zero

Table 31.

DivIrqReg register (address 05h); reset value: x0h bit allocation

Bit

Symbol

Set2

reserved

MﬁnActIRq

reserved

CRCIRq

reserved

Access

Table 32.

DivIrqReg register bit descriptions

All bits in the DivIrqReg register are cleared by software.

Bit

Symbol

Value Description

Set2

indicates that the marked bits in the DivIrqReg register are set

indicates that the marked bits in the DivIrqReg register are cleared

6 to 5 reserved

reserved for future use

MﬁnActIRq 1

MFIN is active

this interrupt is set when either a rising or falling signal edge is

detected

reserved

reserved for future use

CRCIRq

the CalcCRC command is active and all data is processed

1 to 0 reserved

reserved for future use

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