MFRC522 datasheet(28/96 Pages) NXP

28 / 96 page

MFRC522_33

Product data sheet

PUBLIC

Rev. 3 — 26 October 2009

112133

28 of 96

NXP Semiconductors

MFRC522

Contactless reader IC

• FIFO buffer almost empty warning: Status1Reg register’s LoAlert bit

• FIFO buffer overﬂow warning: ErrorReg register’s BufferOvﬂ bit. The BufferOvﬂ bit can

only be cleared by setting the FIFOLevelReg register’s FlushBuffer bit.

The MFRC522 can generate an interrupt signal when:

• ComIEnReg register’s LoAlertIEn bit is set to logic 1. It activates pin IRQ when

Status1Reg register’s LoAlert bit changes to logic 1.

• ComIEnReg register’s HiAlertIEn bit is set to logic 1. It activates pin IRQ when

Status1Reg register’s HiAlert bit changes to logic 1.

If the maximum number of WaterLevel bytes (as set in the WaterLevelReg register) or less

are stored in the FIFO buffer, the HiAlert bit is set to logic 1. It is generated according to

Equation 3:

(3)

If the number of WaterLevel bytes (as set in the WaterLevelReg register) or less are stored

in the FIFO buffer, the LoAlert bit is set to logic 1. It is generated according to Equation 4:

(4)

8.4 Interrupt request system

The MFRC522 indicates certain events by setting the Status1Reg register’s IRq bit and, if

activated, by pin IRQ. The signal on pin IRQ can be used to interrupt the host using its

interrupt handling capabilities. This allows the implementation of efﬁcient host software.

8.4.1 Interrupt sources overview

Table 18 shows the available interrupt bits, the corresponding source and the condition for

its activation. The ComIrqReg register’s TimerIRq interrupt bit indicates an interrupt set by

the timer unit which is set when the timer decrements from 1 to 0.

The ComIrqReg register’s TxIRq bit indicates that the transmitter has ﬁnished. If the state

changes from sending data to transmitting the end of the frame pattern, the transmitter

unit automatically sets the interrupt bit. The CRC coprocessor sets the DivIrqReg

CRCReady bit = 1.

The ComIrqReg register’s RxIRq bit indicates an interrupt when the end of the received

data is detected. The ComIrqReg register’s IdleIRq bit is set if a command ﬁnishes and

the Command[3:0] value in the CommandReg register changes to idle (see Table 149 on

page 67).

The ComIrqReg register’s HiAlertIRq bit is set to logic 1 when the Status1Reg register’s

HiAlert bit is set to logic 1 which means that the FIFO buffer has reached the level

indicated by the WaterLevel[5:0] bits.

The ComIrqReg register’s LoAlertIRq bit is set to logic 1 when the Status1Reg register’s

LoAlert bit is set to logic 1 which means that the FIFO buffer has reached the level

indicated by the WaterLevel[5:0] bits.

HiAlert

FIFOLength

–

() WaterLevel

≤

LoAlert

FIFOLength

WaterLevel

≤

MFRC522 数据表(PDF) 28 Page - NXP Semiconductors

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