MFRC522 datasheet(79/96 Pages) NXP

79 / 96 page

MFRC522_33

Product data sheet

PUBLIC

Rev. 3 — 26 October 2009

112133

79 of 96

NXP Semiconductors

MFRC522

Contactless reader IC

16. Test information

16.1 Test signals

16.1.1 Self test

The MFRC522 has the capability to perform a digital self test. The self test is started by

using the following procedure:

1. Perform a soft reset.

2. Clear the internal buffer by writing 25 bytes of 00h and implement the Conﬁg

command.

3. Enable the self test by writing 09h to the AutoTestReg register.

4. Write 00h to the FIFO buffer.

5. Start the self test with the CalcCRC command.

6. The self test is initiated.

7. When the self test has completed, the FIFO buffer contains the following 64 bytes:

FIFO buffer byte values for version 90h:

00h, 87h, 98h, 0fh, 49h, FFh, 07h, 19h

BFh, 22h, 30h, 49h, 59h, 63h, ADh, CAh

7Fh, E3h, 4Eh, 03h, 5Ch, 4Eh, 49h, 50h

47h, 9Ah, 37h, 61h, E7h, E2h, C6h, 2Eh

75h, 5Ah, EDh, 04h, 3Dh, 02h, 4Bh, 78h

32h, FFh, 58h, 3Bh, 7Ch, E9h, 00h, 94h

B4h, 4Ah, 59h, 5Bh, FDh, U9h, 29h, DFh

35h, 96h, 98h, 9Eh, 4Fh, 30h, 32h, 8Dh

FIFO buffer byte values for version 91h:

00h, C6h, 37h, D5h, 32h, B7h, 57h, 5Ch

C2h, D8h, 7Ch, 4Dh, D9h, 70h, C7h, 73h

10h, E6h, D2h, AAh, 5Eh, A1h, 3Eh, 5Ah

14h, AFh, 30h, 61h, C9h, 70h, DBh, 2Eh

64h, 22h, 72h, B5h, BDh, 65h, F4h, ECh

22h, BCh, D3h, 72h, 35h, CDh, AAh, 41h

1Fh, A7h, F3h, 53h, 14h, DEh, 7Eh, 02h

D9h, 0Fh, B5h, 5Eh, 25h, 1Dh, 29h, 79h

16.1.2 Test bus

The test bus is used for production tests. The following conﬁguration can be used to

improve the design of a system using the MFRC522. The test bus allows internal signals

to be routed to the digital interface. The test bus comprises two sets of test signals which

are selected using their subaddress speciﬁed in the TestSel2Reg register’s

TestBusSel[4:0] bits. The test signals and their related digital output pins are described in

Table 156 and Table 157.

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