MFRC522 datasheet(32/96 Pages) NXP

32 / 96 page

MFRC522_33

Product data sheet

PUBLIC

Rev. 3 — 26 October 2009

112133

32 of 96

NXP Semiconductors

MFRC522

Contactless reader IC

The clock applied to the MFRC522 provides a time basis for the synchronous system’s

encoder and decoder. The stability of the clock frequency, therefore, is an important factor

for correct operation. To obtain optimum performance, clock jitter must be reduced as

much as possible. This is best achieved using the internal oscillator buffer with the

recommended circuitry.

If an external clock source is used, the clock signal must be applied to pin OSCIN. In this

case, special care must be taken with the clock duty cycle and clock jitter and the clock

quality must be veriﬁed.

8.8 Reset and oscillator start-up time

8.8.1 Reset timing requirements

The reset signal is ﬁltered by a hysteresis circuit and a spike ﬁlter before it enters the

digital circuit. The spike ﬁlter rejects signals shorter than 10 ns. In order to perform a

reset, the signal must be LOW for at least 100 ns.

8.8.2 Oscillator start-up time

If the MFRC522 has been set to a Power-down mode or is powered by a VDDX supply, the

start-up time for the MFRC522 depends on the oscillator used and is shown in Figure 23.

The time (tstartup) is the start-up time of the crystal oscillator circuit. The crystal oscillator

start-up time is deﬁned by the crystal.

The time (td) is the internal delay time of the MFRC522 when the clock signal is stable

before the MFRC522 can be addressed.

The delay time is calculated by:

(6)

The time (tosc) is the sum of td and tstartup.

Fig 23. Oscillator start-up time

1024

µs

--------------

37.74

µs

001aak596

tstartup

tosc

device activation

oscillator

clock stable

clock ready

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