EM357-RTR datasheet(97/240 Pages) ETC2

97 / 240 page

EM351 / EM357

SC_UART2STP selects the number of stop bits in transmitted characters. (Only one stop bit is required in

received characters.) If this bit is clear, characters are transmitted with one stop bit; if set, characters are

transmitted with two stop bits.

SC_UARTPAR controls whether or not received and transmitted characters include a parity bit. If

SC_UARTPAR is clear, characters do not contain a parity bit, otherwise, characters do contain a parity bit.

SC_UARTODD specifies whether transmitted and received parity bits contain odd or even parity. If this bit

is clear, the parity bit is even, and if set, the parity bit is odd. Even parity is the exclusive-or of all of the

data bits, and odd parity is the inverse of the even parity value. SC_UARTODD has no effect if SC_UARTPAR

is clear.

A UART character frame contains, in sequence:

The start bit

The least significant data bit

The remaining data bits

If parity is enabled, the parity bit

The stop bit, or bits, if 2 stop bits are selected.

Figure 8-3 shows the UART character frame format, with optional bits indicated. Depending on the options

chosen for the character frame, the length of a character frame ranges from 9 to 12 bit times.

Note that asynchronous serial data may have arbitrarily long idle periods between characters. When idle,

serial data (TXD or RXD) is held in the high state. Serial data transitions to the low state in the start bit at the

beginning of a character frame.

Figure 8-3. UART Character Frame Format

Idle time

Start

Bit

Data

Bit 0

Data

Bit 1

Data

Bit 2

Data

Bit 3

Data

Bit 4

Data

Bit 5

Data

Bit 6

Data

Bit 7

Parity

Bit

Stop

Bit

Stop

Bit

Start Bit

IdleTime

UART Character Frame Format

(optional sections are in italics)

TXD

RXD

8.6.3

FIFOs

Characters transmitted and received by the UART are buffered in the transmit and receive FIFOs that are both

4 entries deep (see Figure 8-4). When software writes a character to the SC1_DATA register, it is pushed onto

the transmit FIFO. Similarly, when software reads from the SC1_DATA register, the character returned is

pulled from the receive FIFO. If the transmit and receive DMA channels are used, the DMA channels also write

to and read from the transmit and receive FIFOs.

Figure 8-4. UART FIFOs

8-26

120-035X-000D

Preliminary

Receive Shift Register

SC1_DATA (read)

Transmit Shift Register

SC1_DATA (write)

RXD

TXD

Parity/Frame Errors

SC1_UARTSTAT

CPU and DMA

Channel Access

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