EM357-RTR datasheet(45/240 Pages) ETC2

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EM351 / EM357

early warning. When the watchdog is enabled, the timer must be periodically reset by writing to the

WDOG_RESTART register before it expires.

The watchdog timer can be paused when the debugger halts the ARM

® CortexTM-M3. To enable this

functionality, set the bit SLEEPTMR_DBGPAUSE in the SLEEPTMR_CFG register.

If the low-frequency internal RC oscillator (OSCRC) is turned off during deep sleep, CLK1K stops. As a

consequence the watchdog timer stops counting and is effectively paused during deep sleep.

The watchdog enable/disable bits are protected from accidental change by requiring a two step process. To

enable the watchdog timer the application must first write the enable code 0xEABE to the WDOG_KEY register

and then set the WDOG_ENABLE bit in the WDOG_CFG register. To disable the timer the application must

write the disable code 0xDEAD to the WDOG_KEY register and then set the WDOG_DISABLE bit in the

WDOG_CFG register.

6.4.2

Sleep Timer

The EM35x integrates a 32-bit timer dedicated to system timing and waking from sleep at specific times. The

sleep timer can use either the calibrated 1 kHz reference (CLK1K), or the 32 kHz crystal clock (CLK32K). The

default clock source is the internal 1 kHz clock. The sleep timer clock source is chosen with the

SLEEPTMR_CLKSEL bit in the SLEEPTMR_CFG register.

The sleep timer has a prescaler, a divider of the form 2^N, where N can be programmed from 1 to 2^15. This

divider allows for very long periods of sleep to be timed. Ember software’s default configuration is to use the

prescaler to always produce a 1024 Hz sleep timer tick. The timer provides two compare outputs and wrap

detection, all of which can be used to generate an interrupt or a wake up event.

The sleep timer is paused when the debugger halts the ARM

® CortexTM-M3. No additional register bit must be

set.

To save current during deep sleep, the low-frequency internal RC oscillator (OSCRC) can be turned off. If

OSCRC is turned off during deep sleep and a low-frequency 32.768 kHz crystal oscillator is not being used,

then the sleep timer will not operate during deep sleep and sleep timer wake events cannot be used to wake

up the EM35x.

6.4.3

Event Timer

The SysTick timer is an ARM® standard system timer in the NVIC. The SysTick timer can be clocked from either

the FCLK (the clock going into the CPU) or the Sleep Timer clock. FCLK is either the SYSCLK or PCLK as

selected by CPU_CLKSEL register (see the Clock Switching section).

6.5

Power Management

The EM35x’s power management system is designed to achieve the lowest deep sleep current consumption

possible while still providing flexible wakeup sources, timer activity, and debugger operation. The EM35x has

four main sleep modes:

Idle Sleep: Puts the CPU into an idle state where execution is suspended until any interrupt occurs. All

power domains remain fully powered and nothing is reset.

Deep Sleep 1: The primary deep sleep state. In this state, the core power domain is fully powered down

and the sleep timer is active

Deep Sleep 2: The same as Deep Sleep 1 except that the sleep timer is inactive to save power. In this

mode the sleep timer cannot wake up the EM35x.

Deep Sleep 0 (also known as Emulated Deep Sleep): The chip emulates a true deep sleep without powering

down the core domain. Instead, the core domain remains powered and all peripherals except the system

debug components (ITM, DWT, FPB, NVIC) are held in reset. The purpose of this sleep state is to allow

6-10

120-035X-000D

Preliminary

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