EM357-RTR datasheet(37/240 Pages) ETC2

37 / 240 page

EM351 / EM357

6.1

Power domains

The EM35x contains three power domains:

An “always-on domain” containing all logic and analog cells required to manage the EM35x’s power modes,

including the GPIO controller and sleep timer. This domain must remain powered.

A “core domain” containing the CPU, Nested Vectored Interrupt Controller (NVIC), and peripherals. To

save power, this domain can be powered down using a mode called deep sleep.

A “memory domain” containing the RAM and flash memories. This domain is managed by the power

management controller. When in deep sleep, the RAM portion of this domain is powered from the always-

on domain supply to retain the RAM contents while the regulators are disabled. During deep sleep the flash

portion is completely powered down.

6.1.1

Internally regulated power

The preferred and recommended power configuration is to use the internal regulated power supplies to

provide power to the core and memory domains. The internal regulators (VREG_1V25 and VREG_1V8) generate

nominal 1.25 V and 1.8 V supplies. The 1.25 V supply is internally routed to the core domain and to an

external pin. The 1.8 V supply is routed to an external pin where it can be externally routed back into the chip

to supply the memory domain. The internal regulators are described in Chapter 16, Integrated Voltage

Regulator.

When using the internal regulators, the always-on domain must be powered between 2.1 V and 3.6 V at all

four VDD_PADS pins.

When using the internal regulators, the VREG_1V8 regulator output pin (VREG_OUT) must be connected to the

VDD_MEM, VDD_PADSA, VDD_VCO, VDD_RF, VDD_IF, VDD_PRE, and VDD_SYNTH pins.

When using the internal regulators, the VREG_1V25 regulator output and supply requires a connection

between both VDD_CORE pins.

6.1.2

Externally regulated power

Optionally, the on-chip regulators may be left unused, and the core and memory domains may instead be

powered from external supplies. For simplicity, the voltage for the core domain can be raised to nominal

1.8 V, requiring only one external regulator, or the core domain can be powered from the on-chip regulators

while the other domains are powered externally. Note that if the core domain is powered at a higher voltage

(1.8 V instead of 1.25 V) then power consumption increases. A regulator enable signal, REG_EN, is provided for

control of external regulators. This is an open-drain signal that requires an external pull-up resistor. If REG_EN

is not required to control external regulators it can be disabled (see section 7.3, Forced Functions in Chapter

7, GPIO).

Using an external regulator requires the always-on domain to be powered between 1.8 V and 3.6 V at all four

VDD_PADS pins.

When using an external regulator, the VREG_1V8 regulator output pin (VREG_OUT) must be left unconnected.

When using an external regulator, this external nominal 1.8 V supply has to be connected to both VDD_CORE

pins and to the VDD_MEM, VDD_PADSA, VDD_VCO, VDD_RF, VDD_IF, VDD_PRE and VDD_SYNTH pins.

6.2

Resets

The EM35x resets are generated from a number of sources. Each of these reset sources feeds into central reset

detection logic that causes various parts of the system to be reset depending on the state of the system and

the nature of the reset event.

6-2

120-035X-000D

Preliminary

EM357-RTR 数据表(PDF) 37 Page - List of Unclassifed Manufacturers

EM357-RTR 数据表(HTML) 37 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载