EM357-RTR datasheet(88/240 Pages) ETC2

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EM351 / EM357

condition until the receive FIFO is drained. Once the DMA marks a receive error, two conditions will clear the

error indication: setting the appropriate SC_TX/RXDMARST bit in the SCx_DMACTRL register, or loading the

appropriate DMA buffer after it has unloaded.

Receiving a character causes the serial transmission of a character pulled from the transmit FIFO. When the

transmit FIFO is empty, a transmit underrun is detected (no data in transmit FIFO) and the INT_SCTXUND bit in

the INT_SCxFLAG register is set. Because no character is available for serialization, the SPI serializer

retransmits the last transmitted character or a busy token (0xFF), determined by the SC_SPIRPT bit in the

SCx_SPICFG register.

When the transmit FIFO and the serializer are both empty, writing a character to the transmit FIFO clears the

SC_SPITXIDLE bit in the SCx_SPISTAT register. This indicates that not all characters have been transmitted. If

characters are written to the transmit FIFO until it is full, the SC_SPITXFREE bit in the SCx_SPISTAT register is

cleared. Shifting out a transmit character to the MISO pin causes the SC_SPITXFREE bit in the SCx_SPISTAT

SC_SPITXIDLE bit in the SCx_SPISTAT register is set.

The SPI slave controller must guarantee that there is time to move new transmit data from the transmit FIFO

into the hardware serializer. To provide sufficient time, the SPI slave controller inserts a byte of padding at

the start of every new string of transmit data. Whenever the transmit FIFO is empty and data is placed into

the transmit FIFO, either manually or through DMA, the SPI hardware inserts a byte of padding onto the front

of the transmission as if this byte was placed there by software. The value of the byte of padding that is

inserted is selected by the SC_SPIRPT bit in the SCx_SPICFG register.

8.4.4

DMA

The DMA Channels section describes how to configure and use the serial receive and transmit DMA channels.

When using the receive DMA channel and nSSEL transitions to the high (deasserted) state, the active buffer’s

receive DMA count register (SCx_RXCNTA/B) is saved in the SCx_RXCNTSAVED register. SCx_RXCNTSAVED is

only written the first time nSSEL goes high after a buffer has been loaded. Subsequent rising edges set a status

bit but are otherwise ignored. The 3-bit field SC_RXSSEL in the SCx_DMASTAT register records what, if

anything, was saved to the SCx_RXCNTSAVED register, and whether or not another rising edge occurred on

nSSEL.

8.4.5

Interrupts

SPI slave controller second-level interrupts are generated on the following events:

Transmit FIFO empty and last character shifted out (depending on SCx_INTMODE, either the 0 to 1

transition or the high level of SC_SPITXIDLE)

Transmit FIFO changed from full to not full (depending on SCx_INTMODE, either the 0 to 1 transition or the

high level of SC_SPITXFREE)

Receive FIFO changed from empty to not empty (depending on SCx_INTMODE, either the 0 to 1 transition

or the high level of SC_SPIRXVAL)

Transmit DMA buffer A/B complete (1 to 0 transition of SC_TXACTA/B)

Receive DMA buffer A/B complete (1 to 0 transition of SC_RXACTA/B)

Received and lost character while receive FIFO was full (receive overrun error)

Transmitted character while transmit FIFO was empty (transmit underrun error)

To enable CPU interrupts, set desired interrupt bits in the second-level INT_SCxCFG register, and also enable

the top-level SCx interrupt in the NVIC by writing the INT_SCx bit in the INT_CFGSET register.

8-17

120-035X-000D

Preliminary

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