EM357-RTR datasheet(39/240 Pages) ETC2

39 / 240 page

EM351 / EM357

6.2.1.3

Watchdog Reset

The EM35x contains a watchdog timer (see also the Watchdog Timer section) that is clocked by the internal

1 kHz timing reference. When the timer expires it generates the reset source WATCHDOG_RESET to the Reset

Generation module.

6.2.1.4

Software Reset

The ARM® CortexTM-M3 CPU can initiate a reset under software control. This is indicated with the reset source

SYSRESETREQ to the Reset Generation module.

6.2.1.5

Option Byte Error

The flash memory controller contains a state machine that reads configuration information from the

information blocks in the flash at system start time. An error check is performed on the option bytes that are

read from flash and, if the check fails, an error is signaled that provides the reset source OPT_BYTE_ERROR to

the Reset Generation module.

If an option byte error is detected, the system restarts and the read and check process is repeated. If the

error is detected again the process is repeated but stops on the 3rd failure. The system is then placed into an

emulated deep sleep where recovery is possible. In this state, flash memory readout protection is forced

active to prevent secure applications from being compromised.

6.2.1.6

Debug Reset

The Serial Wire/JTAG Interface (SWJ) provides access to the SWJ Debug Port (SWJ-DP) registers. By setting

the register bit CDBGRSTREQ in the SWJ-DP, the reset source CDBGRSTREQ is provided to the Reset

Generation module.

6.2.1.7

JRST

One of the EM35x’s pins can function as the JTAG reset, conforming to the requirements of the JTAG

standard. This input acts independently of all other reset sources and, when asserted, does not reset any on-

chip hardware except for the JTAG TAP. If the EM35x is in the Serial Wire mode or if the SWJ is disabled, this

input has no effect.

6.2.1.8

Deep Sleep Reset

The Power Management module informs the Reset Generation module of entry into and exit from the deep

sleep states. The deep sleep reset is applied in the following states: before entry into deep sleep, while

removing power from the memory and core domain, while in deep sleep, while waking from deep sleep, and

while reapplying power until reliable power levels have been detect by POR LV.

The Power Management module allows a special emulated deep sleep state that retains memory and core

domain power while in deep sleep.

6.2.2

Reset Recording

The EM35x records the last reset condition that generated a restart to the system. The reset conditions

recorded are:

POWER_HV

always-on domain power supply failure

POWER_LV

core or memory domain power supply failure

RSTB

nRESET pin asserted

W_DOG

watchdog timer expired

SW_RST

software reset by SYSERSETREQ from ARM

® CortexTM-M3 CPU

WAKE_UP_DSLEEP

wake-up from deep sleep

OPT_BYTE_FAIL

error check failed when reading option bytes from flash

6-4

120-035X-000D

Preliminary

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