EM357-RTR datasheet(80/240 Pages) ETC2

80 / 240 page

EM351 / EM357

last transmitted character or to transmit a busy token (0xFF), which is determined by the SC_SPIRPT bit in the

SCx_SPICFG register. This functionality can only be enabled or disabled when the transmit FIFO is empty and

the transmit serializer is idle, indicated by a cleared SC_SPITXIDLE bit in the SCx_SPISTAT register.

Every time an automatic character transmission starts, a transmit underrun is detected as there is no data in

transmit FIFO, and the INT_SCTXUND bit in the INT_SC2FLAG register is set. After automatic character

transmission is disabled, no more new characters are received. The receive FIFO holds characters just

received.

Note:

The Receive DMA complete event does not always mean the receive FIFO is empty.

The DMA Channels section describes how to configure and use the serial receive and transmit DMA channels.

8.3.4

Interrupts

SPI master controller second-level interrupts are generated by the following events:

Transmit FIFO empty and last character shifted out (depending on SCx_INTMODE, either the 0 to 1

transition or the high level of SC_SPITXIDLE)

Transmit FIFO changed from full to not full (depending on SCx_INTMODE, either the 0 to 1 transition or the

high level of SC_SPITXFREE)

Receive FIFO changed from empty to not empty (depending on SCx_INTMODE, either the 0 to 1 transition

or the high level of SC_SPIRXVAL)

Transmit DMA buffer A/B complete (1 to 0 transition of SC_TXACTA/B)

Receive DMA buffer A/B complete (1 to 0 transition of SC_RXACTA/B)

Received and lost character while receive FIFO was full (receive overrun error)

Transmitted character while transmit FIFO was empty (transmit underrun error)

To enable CPU interrupts, set the desired interrupt bits in the second-level INT_SCxCFG register, and enable

the top-level SCx interrupt in the NVIC by writing the INT_SCx bit in the INT_CFGSET register.

8-9

120-035X-000D

Preliminary

EM357-RTR 数据表(PDF) 80 Page - List of Unclassifed Manufacturers