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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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EM357-RTR 数据表(PDF) 87 Page - List of Unclassifed Manufacturers |
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EM357-RTR 数据表(HTML) 87 Page - List of Unclassifed Manufacturers |
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87 / 240 page  EM351 / EM357 The SPI slave controller supports various frame formats depending upon the clock polarity (SC_SPIPOL), clock phase (SC_SPIPHA), and direction of data (SC_SPIORD) (see Table 8-6). The SC_SPIPOL, SC_SPIPHA, and SC_SPIORD bits are defined within the SCx_SPICFG registers. Table 8-6. SPI Slave Formats SCx_SPICFG SC_SPIxxx 1 MST ORD PHA POL Frame Format 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 - - Same as above except LSB first instead of MSB first 1 The notation xxx means that the corresponding column header below is inserted to form the field name. 8.4.3 Operation When the slave select (nSSEL) signal is asserted by the master, SPI transmit data is driven to the output pin MISO, and SPI data is received from the input pin MOSI. The nSSEL pin has to be asserted to enable the transmit serializer to drive data to the output signal MISO. A falling edge on nSSEL resets the SPI slave shift registers. Characters transmitted and received by the SPI slave controller are buffered in the transmit and receive FIFOs that are both 4 entries deep. When software writes a character to the SCx_DATA register, it is pushed onto the transmit FIFO. Similarly, when software reads from the SCx_DATA register, the character returned is pulled from the receive FIFO. If the transmit and receive DMA channels are used, the DMA channels also write to and read from the transmit and receive FIFOs. Characters received are stored in the receive FIFO. Receiving characters sets the SC_SPIRXVAL bit in the SCx_SPISTAT register, to indicate that characters can be read from the receive FIFO. Characters received while the receive FIFO is full are dropped, and the SC_SPIRXOVF bit in the SCx_SPISTAT register is set. The receive FIFO hardware generates the INT_SCRXOVF interrupt, but the DMA register will not indicate the error 8-16 120-035X-000D Preliminary |
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