EM357-RTR datasheet(124/240 Pages) ETC2

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EM351 / EM357

update event (UEV), depending on the auto-reload buffer enable bit (TIM_ARBE) in the TIMx_CR1 register. The

UEV is generated when both the counter reaches the overflow (or underflow when down-counting) and when

the TIM_UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. UEV generation is

described in detail for each configuration.

The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit

(TIM_CEN) in the TIMx_CR1 register is set. Refer also to the slave mode controller description in the Timers

and External Trigger Synchronization section to get more details on counter enabling.

Note that the actual counter enable signal CNT_EN is set one clock cycle after TIM_CEN.

Note:

When the EM35x enters debug mode and the ARM® CortexTM-M3 core is halted, the counters continue to

run normally.

9.3.1.1

Prescaler

The prescaler can divide the counter clock frequency by power of two from 1 through 32768. It is based on a

16-bit counter controlled through the 4-bit TIM_PSCEXP bit field in the TIMx_PSC register. The factor by which

the counter is divided is two raised to the power TIM_PSCEXP (2TIM_PSCEXP).

It can be changed on the fly as this control register is buffered. The new prescaler ratio is used starting at the

next UEV.

Figure 9-2 gives an example of the counter behavior when the prescaler ratio is changed on the fly.

Figure 9-2. Counter Timing Diagram with Prescaler Division Change from 1 to 4

9.3.2

Counter Modes

9.3.2.1

Up-Counting Mode

In up-counting mode, the counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register),

then restarts from 0 and generates a counter overflow event.

A UEV can be generated at each counter overflow, by setting the TIM_UG bit in the TIMx_EGR register, or by

using the slave mode controller.

Software can disable the UEV by setting the TIM_UDIS bit in the TIMx_CR1 register, to avoid updating the

shadow registers while writing new values in the buffer registers. No UEV will occur until the TIM_UDIS bit is

written to 0. Both the counter and the prescaler counter restart from 0, but the prescale rate does not

change. In addition, if the TIM_URS bit in the TIMx_CR1 register is set, setting the TIM_UG bit generates a UEV

9-4

120-035X-000D

Preliminary

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