EM357-RTR datasheet(189/240 Pages) ETC2

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EM351 / EM357

ADC_CFG

ADC Configuration Register

Address: 0x4000D004 Reset: 0x00001800

ADC_PERIOD

ADC_HVSELP

ADC_HVSELN

ADC_MUXP

ADC_MUXN

ADC_1MHZCLK

ADC_CFGRSVD

ADC_ENABLE

Bitname

Bitfield

Access

Description

ADC_PERIOD

[15:13]

ADC sample time in clocks and the equivalent significant bits in the conversion.

0: 32 clocks (7 bits).

1: 64 clocks (8 bits).

2: 128 clocks (9 bits).

3: 256 clocks (10 bits).

4: 512 clocks (11 bits).

5: 1024 clocks (12 bits).

6: 2048 clocks (13 bits).

7: 4096 clocks (14 bits).

ADC_HVSELP

[12]

Select voltage range for the P input channel.

0: Low voltage range (input buffer disabled).

1: High voltage range (input buffer enabled).

ADC_HVSELN

[11]

Select voltage range for the N input channel.

0: Low voltage range (input buffer disabled).

1: High voltage range (input buffer enabled).

ADC_MUXP

[10:7]

Input selection for the P channel.

0x0: PB5 pin.

0x1: PB6 pin.

0x2: PB7 pin.

0x3: PC1 pin.

0x4: PA4 pin.

0x5: PA5 pin.

0x8: GND (0V) (not for high voltage range).

0x9: VREF/2 (0.6V).

0xA: VREF (1.2V).

0xB: VDD_PADSA/2 (0.9V) (not for high voltage range).

0x6, 0x7, 0xC-0xF: reserved.

ADC_MUXN

[6:3]

Input selection for the N channel.

Refer to ADC_MUXP above for choices.

ADC_1MHZCLK

[2]

Select ADC clock: 0 = 6 MHz, 1 = 1 MHz.

ADC_CFGRSVD

[1]

Reserved: this bit must always be set to 0.

ADC_ENABLE

[0]

Enable the ADC: write 1 to enable continuous conversions, write 0 to stop.

When the ADC is started the first conversion takes twice the usual number of clocks plus

21 microseconds. If anything in this register is modified while the ADC is running, the next

conversion takes twice the usual number of clocks.

10-14

120-035X-000D

Preliminary

EM357-RTR 数据表(PDF) 189 Page - List of Unclassifed Manufacturers

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