ADP5050ACPZ-R7 datasheet(37/60 Pages) AD

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Data Sheet

ADP5050

Rev. 0 | Page 37 of 60

CIRCUIT BOARD LAYOUT RECOMMENDATIONS

Good circuit board layout is essential to obtain the best perfor-

mance from the ADP5050 (see Figure 65). Poor layout can affect

the regulation and stability of the part, as well as the electro-

magnetic interference (EMI) and electromagnetic compatibility

(EMC) performance. Refer to the following guidelines for a good

PCB layout.

•

Place the input capacitor, inductor, MOSFET, output

capacitor, and bootstrap capacitor close to the IC.

•

Use short, thick traces to connect the input capacitors

to the PVINx pins, and use dedicated power ground to

connect the input and output capacitor grounds to

minimize the connection length.

•

Use several high current vias, if required, to connect

PVINx, PGNDx, and SWx to other power planes.

•

Use short, thick traces to connect the inductors to the

SWx pins and the output capacitors.

•

Ensure that the high current loop traces are as short and

wide as possible. Figure 64 shows the high current path.

•

Maximize the amount of ground metal for the exposed

pad, and use as many vias as possible on the component

side to improve thermal dissipation.

•

Use a ground plane with several vias connecting to the com-

ponent side ground to further reduce noise interference on

sensitive circuit nodes.

•

Place the decoupling capacitors close to the VREG and

VDD pins.

•

Place the frequency setting resistor close to the RT pin.

•

Place the feedback resistor divider close to the FBx pin. In

addition, keep the FBx traces away from the high current

traces and the switch node to avoid noise pickup.

•

Use Size 0402 or 0603 resistors and capacitors to achieve

the smallest possible footprint solution on boards where

space is limited.

VIN

VOUT

PVINx

ENx

GND

BSTx

SWx

ADP5050

DLx

FBx

Figure 64. Typical Circuit with High Current Traces Shown in Blue

Figure 65. Typical PCB Layout for the ADP5050

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