ADP5050ACPZ-R7 datasheet(23/60 Pages) AD

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Data Sheet

ADP5050

Rev. 0 | Page 23 of 60

SOFT START

The buck regulators in the ADP5050 include soft start circuitry

that ramps the output voltage in a controlled manner during

startup, thereby limiting the inrush current. The soft start time

is typically fixed at 2 ms for each buck regulator when the SS12

and SS34 pins are tied to VREG.

To set the soft start time to a value of 2 ms, 4 ms, or 8 ms, connect

a resistor divider from the SS12 or SS34 pin to the VREG pin and

ground (see Figure 49). This configuration may be required to

accommodate a specific start-up sequence or an application with

a large output capacitor.

LEVEL DETECTOR

AND DECODER

VREG

TOP

RESISTOR

BOTTOM

RESISTOR

SS12

SS34

ADP5050

Figure 49. Level Detector Circuit for Soft Start

The SS12 pin can be used to program the soft start time and

parallel operation for Channel 1 and Channel 2. The SS34 pin

can be used to program the soft start time for Channel 3 and

Channel 4. Table 10 provides the values of the resistors needed

to set the soft start time.

Table 10. Soft Start Time Set by the SS12 and SS34 Pins

Soft Start Time

RTOP (kΩ) RBOT (kΩ) Channel 1 Channel 2 Channel 3 Channel 4

N/A

2 ms

100

600

2 ms

Parallel

2 ms

4 ms

200

500

2 ms

8 ms

2 ms

8 ms

300

400

4 ms

2 ms

4 ms

2 ms

400

300

4 ms

500

200

8 ms

2 ms

4 ms

8 ms

600

100

8 ms

Parallel

8 ms

2 ms

N/A

8 ms

PARALLEL OPERATION

The ADP5050 supports two-phase parallel operation of Channel 1

and Channel 2 to provide a single output with up to 8 A of current.

To configure Channel 1 and Channel 2 as a two-phase single output

in parallel operation, do the following (see Figure 50):

•

Use the SS12 pin to select parallel operation as specified

in Table 10.

•

Leave the COMP2 pin open.

•

Use the FB1 pin to set the output voltage.

•

Connect the FB2 pin to ground (FB2 is ignored).

•

Connect the EN2 pin to ground (EN2 is ignored).

CHANNEL 1

BUCK REGULATOR

(4A)

CHANNEL 2

BUCK REGULATOR

(4A)

FB1

PVIN1

VOUT

(UP TO 8A)

VIN

EN1

EN2

COMP1

SS12

SW1

FB2

SW2

PVIN2

COMP2

VREG

Figure 50. Parallel Operation for Channel 1 and Channel 2

When Channel 1 and Channel 2 are operated in the parallel

configuration, configure the channels as follows:

•

Set the input voltages and current-limit settings for

Channel 1 and Channel 2 to the same values.

•

Operate both channels in forced PWM mode.

Bits pertaining to Channel 2 in the configuration registers

cannot be used. These bits include CH2_ON in Register 1,

VID2 in Register 3, OVP2_ON and SCP2_ON in Register 7,

PHASE2 in Register 8, and PWRG2 in Register 13.

Current balance in parallel configuration is well regulated by

the internal control loop. Figure 51 shows the typical current

balance matching in the parallel output configuration.

TOTAL OUTPUT LOAD (A)

CH1

CH2

IDEAL

Figure 51. Current Balance in Parallel Output Configuration,

VIN = 12 V, VOUT = 1.2 V, fSW = 600 kHz, FPWM Mode

STARTUP WITH PRECHARGED OUTPUT

The buck regulators in the ADP5050 include a precharged

start-up feature to protect the low-side FETs from damage

during startup. If the output voltage is precharged before the

regulator is turned on, the regulator prevents reverse inductor

current—which discharges the output capacitor—until the

internal soft start reference voltage exceeds the precharged

voltage on the feedback (FBx) pin.

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