ADP5050ACPZ-R7 datasheet(19/60 Pages) AD

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Data Sheet

ADP5050

Rev. 0 | Page 19 of 60

THEORY OF OPERATION

The ADP5050 is a micropower management unit that combines

four high performance buck regulators with a 200 mA low dropout

(LDO) regulator in a 48-lead LFCSP package to meet demanding

performance and board space requirements. The device enables

direct connection to high input voltages up to 15 V with no pre-

regulators to make applications simpler and more efficient.

BUCK REGULATOR OPERATIONAL MODES

PWM Mode

In pulse-width modulation (PWM) mode, the buck regulators

in the ADP5050 operate at a fixed frequency; this frequency is

set by an internal oscillator that is programmed by the RT pin.

At the start of each oscillator cycle, the high-side MOSFET turns

on and sends a positive voltage across the inductor. The inductor

current increases until the current-sense signal exceeds the peak

inductor current threshold that turns off the high-side MOSFET;

this threshold is set by the error amplifier output.

During the high-side MOSFET off time, the inductor current

decreases through the low-side MOSFET until the next oscillator

clock pulse starts a new cycle. The buck regulators in the ADP5050

regulate the output voltage by adjusting the peak inductor current

threshold.

PSM Mode

To achieve higher efficiency, the buck regulators in the ADP5050

smoothly transition to variable frequency power save mode (PSM)

operation when the output load falls below the PSM current

threshold. When the output voltage falls below regulation, the

buck regulator enters PWM mode for a few oscillator cycles until

the voltage increases to within regulation. During the idle time

between bursts, the MOSFET turns off, and the output capacitor

supplies all the output current.

The PSM comparator monitors the internal compensation node,

which represents the peak inductor current information. The

average PSM current threshold depends on the input voltage

(VIN), the output voltage (VOUT), the inductor, and the output

capacitor. Because the output voltage occasionally falls below

regulation and then recovers, the output voltage ripple in PSM

operation is larger than the ripple in the forced PWM mode of

operation under light load conditions.

Forced PWM and Automatic PWM/PSM Modes

The buck regulators can be configured to always operate in

PWM mode using the SYNC/MODE pin and the I2C interface.

In forced PWM (FPWM) mode, the regulator continues to

operate at a fixed frequency even when the output current is

below the PWM/PSM threshold. In PWM mode, efficiency is

lower compared to PSM mode under light load conditions. The

low-side MOSFET remains on when the inductor current falls

to less than 0 A, causing the ADP5050 to enter continuous

conduction mode (CCM).

The buck regulators can be configured to operate in automatic

PWM/PSM mode using the SYNC/MODE pin and the I2C

interface. In automatic PWM/PSM mode, the buck regulators

operate in either PWM mode or PSM mode, depending on the

output current. When the average output current falls below the

PWM/PSM threshold, the buck regulator enters PSM mode

operation; in PSM mode, the regulator operates with a reduced

switching frequency to maintain high efficiency. The low-side

MOSFET turns off when the output current reaches 0 A,

causing the regulator to operate in discontinuous mode (DCM).

The user can alternate between forced PWM (FPWM) mode

and automatic PWM/PSM mode during operation. The flexible

configuration capability during operation of the device enables

efficient power management.

When a logic high level is applied to the SYNC/MODE pin (or

when SYNC/MODE is configured as a clock input or output),

the operational mode of each channel is set by the PSMx_ON

bit in Register 6. A value of 0 for the PSMx_ON bit configures

the channel for forced PWM mode; a value of 1 configures the

channel for automatic PWM/PSM mode.

When a logic low level is applied to the SYNC/MODE pin,

the operational mode of all four buck regulators is automatic

PWM/PSM mode, and the settings of the PSMx_ON bits in

Table 8 describes the function of the SYNC/MODE pin in

setting the operational mode of the device.

Table 8. Configuring the Mode of Operation Using the

SYNC/MODE Pin

Mode of Operation for Each Channel

High

Specified by the PSMx_ON bit setting

in Register 6 (0 = forced PWM mode;

1 = automatic PWM/PSM mode)

Clock Input/Output

Specified by the PSMx_ON bit setting

in Register 6 (0 = forced PWM mode;

1 = automatic PWM/PSM mode)

Low

Automatic PWM/PSM mode (PSMx_ON

bit settings in Register 6 are ignored)

For example, with the SYNC/MODE pin high, write 1 to the

PSM4_ON bit in Register 6 to configure automatic PWM/PSM

mode operation for Channel 4, and write 0 to the PSM1_ON,

PSM2_ON, and PSM3_ON bits to configure forced PWM mode

for Channel 1, Channel 2, and Channel 3.

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