ADP5050ACPZ-R7 datasheet(25/60 Pages) AD

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Data Sheet

ADP5050

Rev. 0 | Page 25 of 60

The short-circuit latch-off status can be read from Register 12,

LCH_STATUS. To clear the status bit, write a 1 to the bit (pro-

vided that the fault no longer persists). The status bit is latched

until a 1 is written to the bit or the part is reset by the internal

VDD power-on reset signal. Note that short-circuit latch-off

mode does not work if hiccup protection is disabled.

Overvoltage Latch-Off Mode

Overvoltage latch-off mode is enabled by factory fuse or by

writing a 1 to the OVPx_ON bit in Register 7, LCH_CFG. The

overvoltage latch-off threshold is 124% of the nominal output

voltage level. When the output voltage exceeds this threshold,

the protection circuit detects the overvoltage status and the regu-

lator shuts down. This shutdown (latch-off) condition is cleared

only by reenabling the channel or by resetting the channel

power supply.

Figure 53 shows the overvoltage latch-off detection function.

OUTPUT

VOLTAGE

TIME

LATCH OFF

THIS

REGULATOR

LATCH-OFF

CHx_LCH

WRITE 1

CHx_LCH BIT

124%

NOMINAL OUTPUT

100%

NOMINAL OUTPUT

CHx ON

Figure 53. Overvoltage Latch-Off Detection

The overvoltage latch-off status can be read from Register 12,

LCH_STATUS. To clear the status bit, write a 1 to the bit (pro-

vided that the fault no longer persists). The status bit is latched

until a 1 is written to the bit or the part is reset by the internal

VDD power-on reset signal.

UNDERVOLTAGE LOCKOUT (UVLO)

Undervoltage lockout circuitry monitors the input voltage level of

each buck regulator in the ADP5050. If any input voltage (PVINx

pin) falls below 3.78 V (typical), the corresponding channel is

turned off. After the input voltage rises above 4.2 V (typical), the

soft start period is initiated, and the corresponding channel is

enabled when the ENx pin is high.

Note that a UVLO condition on Channel 1 (PVIN1 pin) has

a higher priority than a UVLO condition on other channels,

which means that the PVIN1 supply must be available before

other channels can be operated.

POWER-GOOD FUNCTION

The ADP5050 includes an open-drain power-good output

(PWRGD pin) that becomes active high when the selected buck

regulators are operating normally. By default, the PWRGD pin

monitors the output voltage on Channel 1. Other channels can

be configured to control the PWRGD pin when the ADP5050

is ordered (see Table 56).

The power-good status of each channel (PWRGx bit) can be

read back via the I2C interface (Register 13, STATUS_RD). A

value of 1 for the PWRGx bit indicates that the regulated out-

put voltage of the buck regulator is above 90.5% (typical) of its

nominal output. When the regulated output voltage of the buck

regulator falls below 87.2% (typical) of its nominal output for a

delay time greater than approximately 50 µs, the PWRGx bit is

set to 0.

The output of the PWRGD pin is the logical AND of the internal

unmasked PWRGx signals. An internal PWRGx signal must be

high for a validation time of 1 ms before the PWRGD pin goes

high; if one PWRGx signal fails, the PWRGD pin goes low with no

delay. The channels that control the PWRGD pin (Channel 1 to

Channel 4) are specified by factory fuse or by setting the appro-

priate bits in Register 11 (PWRGD_MASK) via the I2C interface.

INTERRUPT FUNCTION

The ADP5050 provides an interrupt output (nINT pin) for fault

conditions. During normal operation, the nINT pin is pulled

high (an external pull-up resistor should be used). When a fault

condition occurs, the ADP5050 pulls the nINT pin low to alert

the I2C host processor that a fault condition has occurred.

Six interrupt sources can trigger the nINT pin. By default, no

interrupt sources are configured. To select one or more interrupt

sources to trigger the nINT pin, set the appropriate bits to 1 in

When the nINT pin is triggered, one or more bits in Register 14

(Bits[5:0]) are set to 1. The fault condition that triggered the nINT

pin can be read from Register 14, INT_STATUS (see Table 12).

Table 12. Fault Conditions for Device Interrupt (Register 14)

Interrupt

Description

TEMP_INT

Junction temperature has exceeded the con-

figured threshold (selected in Register 9)

LVIN_INT

PVIN1 voltage has fallen below the configured

threshold (selected in Register 9)

PWRG4_INT

Power-good failure detected on Channel 4

PWRG3_INT

Power-good failure detected on Channel 3

PWRG2_INT

Power-good failure detected on Channel 2

PWRG1_INT

Power-good failure detected on Channel 1

To clear an interrupt, write a 1 to the appropriate bit in Register 14

(INT_STATUS), take all ENx pins low, or reset the part using the

internal VDD power-on reset signal. Reading the interrupt or

writing a 0 to the bit does not clear the interrupt.

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