ADP5050ACPZ-R7 datasheet(22/60 Pages) AD

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ADP5050

Data Sheet

Rev. 0 | Page 22 of 60

Phase Shift

By default, the phase shift between Channel 1 and Channel 2 and

between Channel 3 and Channel 4 is 180° (see Figure 45). This

value provides the benefits of out-of-phase operation by reduc-

ing the input ripple current and lowering the ground noise.

CH2

CH1

(½

fSW

OPTIONAL)

CH4

180° PHASE SHIFT

0° REFERENCE

90° PHASE SHIFT

270° PHASE SHIFT

0°, 90°,180°, OR 270°

ADJUSTABLE

CH3

(½

fSW

OPTIONAL)

Figure 45. Phase Shift Diagram, Four Buck Regulators

For Channel 2 to Channel 4, the phase shift with respect to

Channel 1 can be set to 0˚, 90˚, 180˚, or 270˚ using Register 8,

SW_CFG (see Figure 46). When parallel operation of Channel 1

and Channel 2 is configured, the switching frequency of Channel 2

is locked to a 180˚ phase shift with respect to Channel 1.

CH3 10.0V BW

CH1 10.0V BW

CH4 10.0V BW

CH2 10.0V BW

M400ns

A CH1

7.40V

SW1

SW2

SW3

SW4

Figure 46. I2C Configurable 90˚ Phase Shift Waveforms, Four Buck Regulators

SYNCHRONIZATION INPUT/OUTPUT

The switching frequency of the ADP5050 can be synchronized

to an external clock with a frequency range from 250 kHz to

1.4 MHz. The ADP5050 automatically detects the presence of

an external clock applied to the SYNC/MODE pin, and the

switching frequency transitions smoothly to the frequency of

the external clock. When the external clock signal stops, the

device automatically switches back to the internal clock and

continues to operate.

Note that the internal switching frequency set by the RT pin must

be programmed to a value that is close to the external clock value

for successful synchronization; the suggested frequency differ-

ence is less than ±15% in typical applications.

The SYNC/MODE pin can be configured as a synchronization

clock output by factory fuse or via the I2C interface (Register 10,

HICCUP_CFG). A positive clock pulse with a 50% duty cycle

is generated at the SYNC/MODE pin with a frequency equal to

the internal switching frequency set by the RT pin. There is a

short delay time (approximately 15% of tSW) from the generated

synchronization clock to the Channel 1 switching node.

Figure 47 shows two ADP5050 devices configured for frequency

synchronization mode: one ADP5050 device is configured as

the clock output to synchronize another ADP5050 device. It is

recommended that a 100 kΩ pull-up resistor be used to prevent

logic errors when the SYNC/MODE pin is left floating.

ADP5050

100kΩ

VREG

SYNC/MODE

ADP5050

Figure 47. Two ADP5050 Devices Configured for Synchronization Mode

In the configuration shown in Figure 47, the phase shift between

Channel 1 of the first ADP5050 device and Channel 1 of the

second ADP5050 device is 0˚ (see Figure 48).

CH3 5.00V BW

CH1 2.00V BW

CH2 5.00V BW

M400ns

A CH1

560mV

SW1

AT FIRST

ADP5050

SW1

AT SECOND

ADP5050

SYNC-OUT

AT FIRST

ADP5050

Figure 48. Waveforms of Two ADP5050 Devices Operating

in Synchronization Mode

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