ADP5050ACPZ-R7 datasheet(21/60 Pages) AD

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Data Sheet

ADP5050

Rev. 0 | Page 21 of 60

LOW-SIDE DEVICE SELECTION

The buck regulators in Channel 1 and Channel 2 integrate 4 A

high-side power MOSFETs and low-side MOSFET drivers. The

N-channel MOSFETs selected for use with the ADP5050 must be

able to work with the synchronized buck regulators. In general,

a low RDSON N-channel MOSFET can be used to achieve higher

efficiency; dual MOSFETs in one package (for both Channel 1

and Channel 2) are recommended to save space on the PCB. For

more information, see the Low-Side Power Device Selection

section.

BOOTSTRAP CIRCUITRY

Each buck regulator in the ADP5050 has an integrated bootstrap

regulator. The bootstrap regulator requires a 0.1 µF ceramic capac-

itor (X5R or X7R) between the BSTx and SWx pins to provide

the gate drive voltage for the high-side MOSFET.

ACTIVE OUTPUT DISCHARGE SWITCH

Each buck regulator in the ADP5050 integrates a discharge switch

from the switching node to ground. This switch is turned on when

its associated regulator is disabled, which helps to discharge the

output capacitor quickly. The typical value of the discharge switch

is 250 Ω for Channel 1 to Channel 4.

The discharge switch function can be enabled or disabled for each

channel by factory fuse or by using the I2C interface (Register 6,

OPT_CFG).

PRECISION ENABLING

The ADP5050 has an enable control pin for each regulator,

including the LDO regulator. The enable control pin (ENx)

features a precision enable circuit with a 0.8 V reference voltage.

When the voltage at the ENx pin is greater than 0.8 V, the regulator

is enabled. When the voltage at the ENx pin falls below 0.725 V,

the regulator is disabled. An internal 1 MΩ pull-down resistor

prevents errors if the ENx pin is left floating.

The precision enable threshold voltage allows easy sequencing

of channels within the part, as well as sequencing between the

ADP5050 and other input/output supplies. The ENx pin can also

be used as a programmable UVLO input using a resistor divider

(see Figure 43). For more information, see the Programming the

UVLO Input section.

0.8V

DEGLITCH

TIMER

INTERNAL

ENABLE

ENx

1MΩ

INPUT/OUTPUT

VOLTAGE

ADP5050

Figure 43. Precision Enable Diagram for One Channel

In addition to the ENx pins, the I2C interface (Register 1,

PCTRL) can also be used to enable and disable each channel. The

on/off status of a channel is controlled by the I2C enable bit for

the channel (CHx_ON) and the external hardware enable pin for

the channel (logical AND).

The default value of the I2C enable bit (CHx_ON = 1) specifies

that the channel enable is controlled by the external hardware

enable pin. Pulling the external ENx pin low resets the channel

and forces the corresponding CHx_ON bit to the default value, 1,

to support another startup when the external ENx pin is pulled

high again.

OSCILLATOR

The switching frequency (fSW) of the ADP5050 can be set to a

value from 250 kHz to 1.4 MHz by connecting a resistor from

the RT pin to ground. The value of the RT resistor can be

calculated as follows:

RRT (kΩ) = [14,822/fSW (kHz)]1.081

Figure 44 shows the typical relationship between the switching

frequency (fSW) and the RT resistor. The adjustable frequency

allows users to make decisions based on the trade-off between

efficiency and solution size.

1.6M

1.4M

1.2M

1.0M

800k

600k

400k

200k

RT RESIST

OR (kΩ)

Figure 44. Switching Frequency vs. RT Resistor

For Channel 1 and Channel 3, the frequency can be set to half

the master switching frequency set by the RT pin. This setting

is configured using Register 8 (Bit 7 for Channel 3, and Bit 6 for

Channel 1). If the master switching frequency is less than 250 kHz,

this halving of the frequency for Channel 1 or Channel 3 is not

recommended.

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