ADP5050ACPZ-R7 datasheet(27/60 Pages) AD

27 / 60 page

Data Sheet

ADP5050

Rev. 0 | Page 27 of 60

I2C INTERFACE

The ADP5050 includes an I2C-compatible serial interface for

control of the power management blocks and for readback of

system status (see Figure 57). The I2C interface operates at clock

frequencies of up to 400 kHz.

I2C

SCL

SDA

LEVEL

SHIFTER

VDDIO

VDD

VDDIO

UVLO_VDDIO

TRIM DATA

SCP/OVP

VDDIO

VDD

VDDIO

Figure 57. I2C Interface Block Diagram

Note that the ADP5050 does not respond to general calls. The

ADP5050 accepts multiple masters, but if the device is in read

mode, access is limited to one master until the data transmission

is completed.

The I2C serial interface can be used to access the internal registers

of the ADP5050. For complete information about the ADP5050

registers, see the Register Map section.

SDA AND SCL PINS

The ADP5050 has two dedicated I2C interface pins, SDA and

SCL. SDA is an open-drain line for receiving and transmitting

data. SCL is an input line for receiving the clock signal. Pull up

these pins to the VDDIO supply using external resistors.

Serial data is transferred on the rising edge of SCL. The read

data is generated at the SDA pin in read mode.

I2C ADDRESSES

The default 7-bit I2C chip address for the ADP5050 is 0x48

(1001000 in binary). A different I2C address can be configured

using the optional A0 pin, which can replace the power-good

functionality on Pin 20. (For information about obtaining an

ADP5050 model with Pin 20 functioning as the A0 pin, contact

your local Analog Devices sales or distribution representative.)

The A0 pin allows the use of two ADP5050 devices on the same

I2C communication bus. Figure 58 shows two ADP5050 devices

configured with different I2C addresses using the A0 pin.

SCL

VDDIO

I2C INTERFACE

I2C ADDRESS = 0x48

I2C ADDRESS = 0x49

SDA

SCL

VDDIO

VREG

SDA

Figure 58. Two ADP5050 Devices Configured with Different I2C Addresses

(A0 Function Replaces PWRGD Function on Pin 20)

SELF-CLEAR REGISTER BITS

clear register bits. These bit are cleared automatically when a 1

is written to the status bit. Therefore, it is not necessary to write

a 0 to the status bit to clear it.

ADP5050ACPZ-R7 数据表(PDF) 27 Page - Analog Devices

ADP5050ACPZ-R7 数据表(HTML) 27 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

数据表下载

链接网址

ADP5050ACPZ-R7 数据表(PDF) 27 Page - Analog Devices

ADP5050ACPZ-R7 数据表(HTML) 27 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

数据表 下载

链接网址

数据表下载