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ADP5050ACPZ-R7 数据表(PDF) 39 Page - Analog Devices

部件名 ADP5050ACPZ-R7
功能描述  5-Channel Integrated Power Solution with Quad Buck Regulators and 200 mA LDO Regulator
PDF  60 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP5050ACPZ-R7 数据表(HTML) 39 Page - Analog Devices

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Data Sheet
ADP5050
Rev. 0 | Page 39 of 60
VREG
CHANNEL 2
BUCK REGULATOR
(1.2A/2.5A/4A)
CHANNEL 3
BUCK REGULATOR
(1.2A)
OSCILLATOR
INT VREG
100mA
Q1
Q2
L1
L2
SYNC/MODE
RT
FB1
BST1
SW1
DL1
PGND
DL2
SW2
BST2
FB2
L3
BST3
SW3
FB3
PGND3
ALERT
L4
10µH
6.8µH
2.2µH
1.5µH
BST4
SW4
FB4
PGND4
nINT
VREG
PVIN1
COMP1
EN1
PVIN2
COMP2
EN2
PVIN3
SS34
COMP3
EN3
VDDIO
OPTIONAL
I2C INTERFACE
PVIN4
COMP4
EN4
SCL
SDA
C2
10µF
C1
1.0µF
C4
47µF
C3
0.1µF
C5
10µF
C6
0.1µF
C7
47µF
C8
10µF
C9
0.1µF
C10
22µF
C11
10µF
C12
0.1µF
C13
22µF
12V
VOUT1
VOUT2
FPGA
2.5V/4A
1.2V/100mA
1.5V/1.2A
3.3V/1.2A
1.2V/4A
DDR
TERM. LDO
DDR
MEMORY
FLASH
MEMORY
VCORE
I/O BANK 1
I/O BANK 0
I/O BANK 2
VOUT3
VOUT4
22kΩ
31.6kΩ
22kΩ
PWRGD
SS12
VREG
C0
1.0µF
VDD
CHANNEL 5
200mA LDO
REGULATOR
FB5
EN5
VOUT5
PVIN5
C15
1µF
C14
1µF
VOUT5
ADP5050
CHANNEL 1
BUCK REGULATOR
(1.2A/2.5A/4A)
CHANNEL 4
BUCK REGULATOR
(1.2A)
C16
47µF
C17
47µF
VREG
MGTs
I/O BANK 3
AUXILIARY
VOLTAGE
EXPOSED PAD
I2C
Si7232DN
(16.4mΩ)
5V REG
5V REG
6.81kΩ
2.7nF
10kΩ
2.7nF
10kΩ
2.7nF
6.81kΩ
10kΩ
10.2kΩ
31.6kΩ
10.2kΩ
8.87kΩ
10.2kΩ
4.99kΩ
10kΩ
21.5kΩ
14kΩ
2.7nF
Figure 67. Typical FPGA Application, 600 kHz Switching Frequency, Adjustable Output Model



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