ADP5050ACPZ-R7 datasheet(24/60 Pages) AD

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ADP5050

Data Sheet

Rev. 0 | Page 24 of 60

CURRENT-LIMIT PROTECTION

The buck regulators in the ADP5050 include peak current-limit

protection circuitry to limit the amount of positive current flowing

through the high-side MOSFET. The peak current limit on the

power switch limits the amount of current that can flow from the

input to the output. The programmable current-limit threshold

feature allows for the use of small size inductors for low current

applications.

To configure the current-limit threshold for Channel 1, connect

a resistor from the DL1 pin to ground; to configure the current-

limit threshold for Channel 2, connect another resistor from the

DL2 pin to ground. Table 11 lists the peak current-limit threshold

settings for Channel 1 and Channel 2.

Table 11. Peak Current-Limit Threshold Settings

for Channel 1 and Channel 2

RILIM1 or RILIM2

Typical Peak Current-Limit Threshold

Floating

4.4 A

47 kΩ

2.63 A

22 kΩ

6.44 A

The buck regulators in the ADP5050 include negative current-

limit protection circuitry to limit certain amounts of negative

current flowing through the low-side MOSFET.

FREQUENCY FOLDBACK

The buck regulators in the ADP5050 include frequency fold-

back to prevent output current runaway when a hard short

occurs on the output. Frequency foldback is implemented

as follows:

•

If the voltage at the FBx pin falls below half the target

output voltage, the switching frequency is reduced by half.

•

If the voltage at the FBx pin falls again to below one-fourth

the target output voltage, the switching frequency is reduced

to half its current value, that is, to one-fourth of fSW.

The reduced switching frequency allows more time for the

inductor current to decrease, but also increases the ripple cur-

rent during peak current regulation. This results in a reduction

in average current and prevents output current runaway.

Pulse Skip Mode Under Maximum Duty Cycle

Under maximum duty cycle conditions, frequency foldback

maintains the output in regulation. If the maximum duty cycle

is reached—for example, when the input voltage decreases—the

PWM modulator skips every other PWM pulse, resulting in a

switching frequency foldback of one-half. If the duty cycle increases

further, the PWM modulator skips two of every three PWM pulses,

resulting in a switching frequency foldback to one-third of the

switching frequency. Frequency foldback increases the effective

maximum duty cycle, thereby decreasing the dropout voltage

between the input and output voltages.

HICCUP PROTECTION

The buck regulators in the ADP5050 include a hiccup mode for

overcurrent protection (OCP). When the peak inductor current

reaches the current-limit threshold, the high-side MOSFET turns

off and the low-side MOSFET turns on until the next cycle.

When hiccup mode is active, the overcurrent fault counter is

incremented. If the overcurrent fault counter reaches 15 and

overflows (indicating a short-circuit condition), both the high-

side and low-side MOSFETs are turned off. The buck regulator

remains in hiccup mode for a period equal to seven soft start

cycles and then attempts to restart from soft start. If the short-

circuit fault has cleared, the regulator resumes normal operation;

otherwise, it reenters hiccup mode after the soft start.

Hiccup protection is masked during the initial soft start cycle to

enable startup of the buck regulator under heavy load conditions.

Note that careful design and proper component selection are

required to ensure that the buck regulator recovers from hiccup

mode under heavy loads. The HICCUPx_OFF bits in Register 10

can be used to disable hiccup protection for each buck regulator.

When hiccup protection is disabled, the frequency foldback feature

is still available for overcurrent protection.

LATCH-OFF PROTECTION

The buck regulators in the ADP5050 have an optional latch-off

mode to protect the device from serious problems such as short-

circuit and overvoltage conditions. Latch-off mode can be enabled

via the I2C interface or by factory fuse.

Short-Circuit Latch-Off Mode

Short-circuit latch-off mode is enabled by factory fuse or by writing

a 1 to the SCPx_ON bit in Register 7, LCH_CFG. When short-

circuit latch-off mode is enabled and the protection circuit detects

an overcurrent status after a soft start, the buck regulator enters

hiccup mode and attempts to restart. If seven continuous restart

attempts are made and the regulator remains in the fault condition,

the regulator is shut down. This shutdown (latch-off) condition is

cleared only by reenabling the channel or by resetting the channel

power supply.

Figure 52 shows the short-circuit latch-off detection function.

OUTPUT

VOLTAGE

TIME

LATCH-OFF

CHx_LCH

LATCH OFF

THIS

REGULATOR

SHORT CIRCUIT DETECTED

BY COUNTER OVERFLOW

PWRGD

7 ×

tSS

SCP LATCH-OFF

FUNCTION ENABLED AFTER

7 RESTART ATTEMPTS

WRITE 1

CHx_LCH BIT

ATTEMPT TO

RESTART

Figure 52. Short-Circuit Latch-Off Detection

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