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ST7LITE25F2 数据表(PDF) 141 Page - STMicroelectronics |
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ST7LITE25F2 数据表(HTML) 141 Page - STMicroelectronics |
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141 / 166 page  ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Electrical characteristics Doc ID 8349 Rev 5 141/166 1. Check that all recommendations related to ICCCLK and reset circuit have been applied (seeTable 2: Device pin description) 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709 and AN2017. If this cannot be done, it is recommended to put a 100nF + 1M Ω pull-down on the RESET pin. 3. The capacitors connected on the RESET pin and also the power supply are key to avoid any startup marginality. In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on the RESET pin with a 5µF to 20µF capacitor.” Note: Please refer to Section 12.2.1: Illegal opcode reset for more details. 13.10 Communication interface characteristics 13.10.1 Serial peripheral interface (SPI) Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO). Table 83. Serial peripheral interface (SPI)(1) 1. Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Symbol Parameter Conditions Min Max Unit fSCK = 1/tc(SCK) SPI clock frequency Master fCPU = 8MHz fCPU/128 = 0.0625 fCPU/4 = 2 MHz Slave fCPU = 8MHz 0fCPU/2 = 4 tr(SCK) tf(SCK) SPI clock rise and fall time − see I/O port pin description tsu(SS) (2) 2. Data based on design simulation and/or characterization results, not tested in production. SS setup time(3) Slave (4 x TCPU) +150 − ns th(SS) (2) SS hold time Slave 120 − tw(SCKH) tw(SCKL) SCK high and low time Master Slave 100 90 − tsu(MI) tsu(SI) Data input setup time Master Slave 100 100 − th(MI) th(SI) Data input hold time Master Slave 100 100 − ta(SO) Data output access time Slave 0 120 tdis(SO) Data output disable time Slave − 240 tv(SO) Data output valid time Slave (after enable edge) − 120 th(SO) Data output hold time 0 − tv(MO) Data output valid time Master (after enable edge) − 120 th(MO) Data output hold time 0 − |
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