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ST7LITE25F2 数据表(PDF) 142 Page - STMicroelectronics

部件名 ST7LITE25F2
功能描述  8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, Timers, SPI
PDF  166 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7LITE25F2 数据表(HTML) 142 Page - STMicroelectronics

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Electrical characteristics
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
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Doc ID 8349 Rev 5
Figure 86. SPI slave timing diagram with CPHA = 0(1)
1.
Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
2.
When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave
mode) has its alternate function capability released. In this case, the pin status depends on the I/O port
configuration.
Figure 87. SPI Slave Timing Diagram with CPHA = 1(1)
1.
Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
2.
When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave
mode) has its alternate function capability released. In this case, the pin status depends on the I/O port
configuration.
3.
Depends on fCPU. For example, if fCPU = 8MHz, then TCPU = 1/ fCPU = 125ns and tSU(SS) = 550ns
SS INPUT
CPHA=0
MOSI INPUT
MISO OUTPUT
CPHA=0
tc(SCK)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
tv(SO)
ta(SO)
tsu(SI)
th(SI)
MSB OUT
MSB IN
BIT6 OUT
LSB IN
LSB OUT
CPOL=0
CPOL=1
tsu(SS)
th(SS)
tdis(SO)
th(SO)
BIT1 IN
(2)
(2)
SS INPUT
CPHA=0
MOSI INPUT
MISO OUTPUT
CPHA=0
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
ta(SO)
tsu(SI)
th(SI)
MSB OUT
BIT6 OUT
LSB OUT
CPOL=0
CPOL=1
tsu(SS)
th(SS)
tdis(SO)
th(SO)
(2)
tc(SCK)
HZ
tv(SO)
MSB IN
LSB IN
BIT1 IN
(2)



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