AD9739-R2-EBZ datasheet(28/48 Pages) AD

28 / 48 page

AD9739

Data Sheet

Rev. B | Page 28 of 48

LVDS DATA PORT INTERFACE

The AD9739 supports input data rates from 1.6 GSPS to 2.5 GSPS

using dual LVDS data ports. The interface is source synchronous

and double data rate (DDR) where the host provides an embedded

data clock input (DCI) at fDAC/4 with its rising and falling edges

aligned with the data transitions. The data format is offset binary;

however, twos complement format can be realized by reversing

the polarity of the MSB differential trace. As shown in Figure 40,

the host feeds the AD9739 with deinterleaved input data into

two 14-bit LVDS data ports (DB0 and DB1) at ½ the DAC clock

rate (that is, fDAC/2). The AD9739 internal data receiver controller

then generates a phase shifted version of DCI to register the

input data on both the rising and falling edges.

DCI

DCO

DIV-BY-4

AD9739

HOST

PROCESSOR

14 × 2

fDATA = fDAC/2

fDCO = fDAC/4

fDAC

fDCI = fDAC/4

14 × 2

1 × 2

EVEN DATA

SAMPLES

ODD DATA

SAMPLES

Figure 40. Recommended Digital Interface Between the AD9739 and

Host Processor

As shown in Figure 41, the DCI clocks edges must be coincident

with the data bit transitions with minimum skew, jitter, and

intersymbol interference. To ensure coincident transitions with the

data bits, the DCI signal should be implemented as an additional

data line with an alternating (010101…) bit sequence from the

same output drivers used for the data. Maximizing the opening

of the eye in both the DCI and data signals improves the reliability

of the data port interface. Differential controlled impedance traces

of equal length (that is, delay) should also be used between the

host processor and AD9739 input to limit bit-to-bit skew.

The maximum allowable skew and jitter out of the host

processor with respect to the DCI clock edge on each LVDS

port is calculated as

MaxSkew + Jitter = Period(ns) − ValidWindow(ps) − Guard

= 800 ps − 344 ps − 100 ps

= 356 ps

where ValidWindow(ps) is represented by tVALID and Guard is

represented by tGUARD in Figure 41.

The minimum specified LVDS valid window is 344 ps, and a

guard band of 100 ps is recommended. Therefore, at the maximum

operating frequency of 2.5 GSPS, the maximum allowable FPGA

and PCB bit skew plus jitter is equal to 356 ps.

For synchronous operation, the AD9739 provides a data clock

output, DCO, to the host at the same rate as DCI (that is, fDAC/4)

to maintain the lowest skew variation between these clock

domains. Since the DCO signal is generated from a separate

clock divider, its phase relationship relative to the fDAC/4 clocks

used by the data receiver controller will vary upon each power-up.

Applications sensitive to this phase ambiguity (resulting in a ±2

DACCLK pipeline variation) should consider using the sync

controller.

The host processor has a worst-case skew between DCO and

DCI that is both implementation and process dependent. This

worst-case skew can also vary an additional 30% over temperature

and supply corners. The delay line within the data receiver

controller can track a ±1.5 ns skew variation after initial lock.

While it is possible for the host to have an internal PLL that

generates a synchronous fDAC/4 from which the DCI signal is

derived, digital implementations that result in the shortest

propagation delays result in the lowest skew variation.

The data receiver controller is used to ensure proper data hand-off

between the host and AD9739 internal digital clock domains.

The circuit shown in Figure 42 functions as a delay lock loop in

which a 90o phase shifted version of the DCI clock input is used

to sample the input data into the DDR receiver registers. This

ensures that the sampling instance occurs in the middle of the

data pattern eyes (assuming matched DCI and DBx[13:0] delays).

Note that, because the DCI delay and sample delay clocks are

derived from the div-by-4 circuitry, this 90° phase relationship

holds as long as the delay settings (that is, DCI_DEL, SMP_DEL)

are also matched.

DB0[13:0]

AND DB1[13:0]

DCI

tVALID

tVALID + tGUARD

2 × 1/fDAC

MAX SKEW

+ JITTER

Figure 41. LVDS Data Port Timing Requirements

AD9739-R2-EBZ 数据表(PDF) 28 Page - Analog Devices

AD9739-R2-EBZ 数据表(HTML) 28 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

数据表下载