AD9739-R2-EBZ datasheet(27/48 Pages) AD

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Data Sheet

AD9739

Rev. B | Page 27 of 48

THEORY OF OPERATION

The AD9739 data receiver controller generates an internal

sampling clock offset by 90° from the DCI to sample the input

data on the DB0 and DB1 ports. When enabled and configured

properly for track mode, it ensures proper data recovery between

the host and the AD9739 clock domains. The data receiver

controller has the ability to track several hundreds of ps of drift

between these clock domains, typically caused by supply and

temperature variation.

Figure 39 shows a top-level functional diagram of the AD9739.

A high performance TxDAC core delivers a signal dependent,

differential current (nominal ±10 mA) to a balanced load

referenced to ground. The frequency of the clock signal

appearing at the AD9739 differential clock receiver, DACCLK,

sets the TxDAC’s update rate. This clock signal, which serves as

the master clock, is routed directly to the TxDAC as well as to a

clock distribution block that generates all critical internal and

external clocks.

As mentioned, the host processor provides the AD9739 with a

deinterleaved data stream such that the DB0 and DB1 data ports

receive alternating samples (that is, odd/even data streams). The

AD9739 data assembler is used to reassemble (that is, multiplex)

the odd/even data streams into their original order before

delivery into the TxDAC for signal reconstruction. The pipeline

delay from a sample being latched into the data port to when it

appears at the DAC output is on the order of 78 (±) DACCLK

cycles. Applications that require matching pipeline delays (that

is, synchronization) between multiple AD9739s can use the

SYNC controller. The SYNC controller phase aligns the outputs

of one or more AD9739 devices (that is,. slaves) to a master

AD9739 device.

DCI

SDO

SDIO

SCLK

DACCLK

DCO

SYNC_OUT

SYNC_IN

CLK DISTRIBUTION

(DIV-BY-4)

SPI

RESET

SYNC-

CONTROLLER

IOUTP

IOUTN

VREF

I120

IRQ

1.2V

DAC BIAS

AD9739

TxDAC

CORE

The AD9739 includes a delay lock loop (DLL) circuit controlled

via a mu controller to optimize the timing hand-off between the

AD9739 digital clock domain and TxDAC core. Besides ensuring

proper data reconstruction, the TxDAC’s ac performance is also

dependent on this critical hand-off between these clock domains

with speeds of up to 2.5 GSPS. Once properly initialized and

configured for track mode, the DLL maintains optimum timing

alignment over temperature, time, and power supply variation.

Figure 39. Functional Block Diagram of the AD9739

A SPI interface is used to configure the various functional blocks as

well as monitor their status for debug purposes. Proper operation

of the AD9739 requires that controller blocks be initialized upon

power-up. A simple SPI initialization routine is used to configure

the controller blocks (see Figure 51 and Figure 52). An IRQ

output signal is available to alert the host should any of the

controllers fall out of lock during normal operation.

The AD9739 includes two 14-bit LVDS data ports (DB0 and

DB1) to reduce the data interface rate to ½ the TxDAC update rate.

The host processor drives deinterleaved data with offset binary

format onto the DB0 and DB1 ports, along with an embedded DCI

clock that is synchronous with the data. Because the interface is

double data rate (DDR), the DCI clock is essentially an alternating

010101……….01010 bit pattern with a frequency equal to ¼ the

TxDAC update rate (fDAC). To simplify synchronization with the

host processor, the AD9739 passes an LVDS clock output (DCO)

that is also equal to the DCI frequency.

The following sections discuss the various functional blocks in

more detail as well as their implications when interfacing to

external ICs and circuitry. While a detailed description of the

various controllers (and associated SPI registers used to configure

and monitor) is also included for completeness, the recommended

SPI boot procedure can be used to ensure reliable operation.

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