AD9739-R2-EBZ datasheet(34/48 Pages) AD

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AD9739

Data Sheet

Rev. B | Page 34 of 48

INTERRUPT REQUESTS

The AD9739 can provide the host processor with an interrupt

request output signal (IRQ) that indicates that one or more of the

AD9739 internal controllers have achieved lock or lost lock. These

controllers include the mu, data receiver, and synchronization

controllers. The host can then poll the IRQ status register

(Register 0x04) to determine which controller has lost lock.

The IRQ output signal is an active high output signal available

on Pin F13. If used, its output should be connected via a 10 kΩ

pull-up resistor to VDD33.

Each IRQ is enabled by setting the enable bits in Register 0x03,

which purposely has the same bit mapping as the IRQ status

bits in Register 0x04. Note that these IRQ status bits are set only

when the controller transitions from a false to true state. Therefore,

it is possible for the x_LCK_IRQ and x_LST_IRQ status bits to

be set when a controller temporarily loses lock but is able to

reestablish lock before the IRQ is serviced by the host. In this

case, the host should validate the present status of the suspect

controller by reading back its current status bits, which are

available in Register 0x21 and/or Register 0x2A. Based on the

status of these bits, the host can take appropriate action, if required,

to reestablish lock. To clear an IRQ after servicing, it is necessary to

reset relevant bits in Register 0x03 by writing 0 followed by

another write of 1 to reenable. A detailed diagram of the

interrupt circuitry is shown in Figure 51.

INT(n)

INT

SOURCE

SPI ISR

READ DATA

(PIN F13)

SPI WRITE

INT

SOURCE

SPI ADDRESS

DATA = 1

IMR

SCLK

SPI

DATA

Figure 51. Interrupt Request Circuitry

It is also possible to use the IRQ during the AD9739 initialization

phase after power-up to determine when the mu and data receiver

controllers have achieved lock. For example, before enabling the

mu controller, the MU_LCK_EN bit (Register 0x03, Bit 2) can be

set and the IRQ output signal monitored to determine when lock

has been established before continuing in a similar manner with

the data receiver controllers. Note that the relevant LCK bit should

be cleared before continuing to the next controller. After all

controllers are locked, the lost lock enable bits (that is, x_LST_EN)

should be set.

Table 29. Interrupt Request Registers

Address (Hex)

Bit

Description

SYNC_LST_EN

SYNC_LCK_EN

MU_LST_EN

MU_LCK_EN

RCV_LST_EN

0x03

RCV_LCK_EN

SYNC_LST_IRQ

SYNC_LCK_IRQ

MU_LST_IRQ

MU_LCK_IRQ

RCV_LST_IRQ

0x04

RCV_LCK_IRQ

SYNC_TRK_ON

SYNC_LST

SYNC_LCK

RCVR_TRK_ON

RCVR_LST

0x21

RCVR_LCK

MU_LST

0x2A

MU_LKD

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