AD9739-R2-EBZ datasheet(18/48 Pages) AD

18 / 48 page

AD9739

Data Sheet

Rev. B | Page 18 of 48

SERIAL PORT INTERFACE (SPI) REGISTER

SPI REGISTER MAP DESCRIPTION

The AD9739 contains a set of programmable registers described

in Table 10 that are used to configure and monitor various internal

parameters. Note the following points when programming the

AD9739 SPI registers:

•

Registers pertaining to similar functions are grouped

together and assigned adjacent addresses.

•

Bits that are undefined within a register should be assigned

a 0 when writing to that register.

•

Registers that are undefined should not be written to.

•

A hardware or software reset is recommended upon

power-up to place SPI registers in a known state.

•

A SPI initialization routine is required as part of the boot

process. See Table 31 and Table 32 for example procedures.

Reset

Issuing a hardware or software reset places the AD9739 SPI

registers in a known state. All SPI registers (excluding 0x00) are

set to their default states as described in Table 10 upon issuing a

reset. After issuing a reset, the SPI initialization process need only

write to registers that are required for the boot process as well as

any other register settings that must be modified, depending on

the target application.

Although the AD9739 does feature an internal power-on-reset

(POR), it is still recommended that a software or hardware reset

be implemented shortly after power-up. The internal reset signal is

derived from a logical OR operation from the internal POR

signal, the RESET pin, and the software reset state. A software

reset can be issued via the reset bit (Register 0x00, Bit 5) by

toggling the bit high then low. Note that, because the MSB/LSB

format may still be unknown upon initial power-up (that is,

internal POR is unsuccessful), it is also recommended that the

bit settings for Bits[7:5] be mirrored onto Bits[2:0] for the

instruction cycle that issues a software reset. A hardware reset

can be issued from a host or external supervisory IC by applying a

high pulse with a minimum width of 40 ns to the RESET pin

(that is, Pin F14). RESET should be tied to VSS if unused.

Table 8. SPI Registers Pertaining to SPI Options

Address (Hex)

Bit

Description

Enable 3-wire SPI

Enable SPI LSB first

0x00

Software reset

SPI OPERATION

The serial port of the AD9739 shown in Figure 34 has a 3- or

4-wire SPI capability, allowing read/write access to all registers

that configure the device’s internal parameters. It provides a

flexible, synchronous serial communications port, allowing easy

interface to many industry-standard microcontrollers and

microprocessors. The 3.3 V serial I/O is compatible with most

synchronous transfer formats, including the Motorola® SPI and

the Intel® SSR protocols.

SDO (PIN H14)

SDIO (PIN G14)

SCLK (PIN H13)

CS (PIN G13)

AD9739

SPI PORT

Figure 34. AD9739 SPI Port

The default 4-wire SPI interface consists of a clock (SCLK), serial

port enable (CS), serial data input (SDIO), and serial data output

(SDO). The inputs to SCLK, CS, and SDIO contain a Schmitt

trigger with a nominal hysteresis of 0.4 V centered about VDD33/2.

The maximum frequency for SCLK is 20 MHz. The SDO pin is

active only during the transmission of data and remains three-

stated at any other time.

A 3-wire SPI interface can be enabled by setting the SDIO_DIR

bit (Register 0x00, Bit 7). This causes the SDIO pin to become

bidirectional such that output data only appears on the SDIO

pin during a read operation. The SDO pin remains three-stated

in a 3-wire SPI interface.

Instruction Header Information

MSB

LSB

R/W

An 8-bit instruction header must accompany each read and write

operation. The MSB is a R/W indicator bit with logic high

indicating a read operation. The remaining seven bits specify

the address bits to be accessed during the data transfer portion.

The eight data bits immediately follow the instruction header

for both read and write operations. For write operations, registers

change immediately upon writing to the last bit of each transfer

byte. CS can be raised after each sequence of eight bits (except

the last byte) to stall the bus. The serial transfer resumes when

CS is lowered. Stalling on nonbyte boundaries resets the SPI.

AD9739-R2-EBZ 数据表(PDF) 18 Page - Analog Devices

AD9739-R2-EBZ 数据表(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

数据表下载