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AM79C978VC/W 数据表(PDF) 216 Page - Advanced Micro Devices |
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AM79C978VC/W 数据表(HTML) 216 Page - Advanced Micro Devices |
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216 / 261 page  216 Am79C978 Am79C978 Programmable Registers (Continued) Register Contents CSR76 RCVRL: RCV Descriptor Ring length CSR78 XMTRL: XMT Descriptor Ring length CSR80 FIFO threshold and DMA burst control (DEFAULT = 2810) 8000 Reserved 4000 Reserved bits [13:12] = RCVFW, Receive FIFO Watermark 0000 Request DMA when 16 bytes are present 1000 Request DMA when 64 bytes are present 2000 Request DMA when 112 bytes are present 3000 Reserved bits [11:10] = XMTSP, Transmit Start Point 0000 Start transmission after 20/36 (No SRAM/SRAM) bytes have been written 0400 Start transmission after 64 bytes have been written 0800 Start transmission after 128 bytes have been written 0C00 Start transmission after 220 max/Full Packet (No SRAM/SRAM with UFLO bit set) bytes have been written bits [9:8] = XMTFW, Transmit FIFO Watermark 0000 Start DMA when 16 write cycles can be made 0100 Start DMA when 32 write cycles can be made 0200 Start DMA when 64 write cycles can be made 0300 Start DMA when 128 write cycles can be made bits [7:0] = DMA Burst Register CSR88~89 Chip ID (Contents = v12626003; v = Version Number) CSR112 Missed Frame Count CSR114 Receive Collision Count CSR116 OnNow Miscellaneous 8000 -- 4000 -- 2000 -- 1000 -- 0800 -- 0400 -- 0200 PME_EN_OVR 0100 LCDET 0080 PMAT 0040 EMPPLBA 0020 MPMAT 0010 MPPEN 0008 RWU_DRIVER 0004 RWU_GATE 0002 RWU_POL 0001 RST_POL CSR122 Receive Frame Alignment Control 8000 -- 4000 -- 2000 -- 1000 -- 0800 -- 0400 -- 0200 -- 0100 -- 0080 -- 0040 -- 0020 -- 0010 -- 0008 -- 0004 -- 0002 -- 0001 RCVALGN CSR124 BMU Test Register (DEFAULT = 0000) 8000 -- 4000 -- 2000 -- 1000 -- 0800 -- 0400 -- 0200 -- 0100 -- 0080 -- 0040 -- 0020 -- 0010 -- 0008 -- 0004 RPA 0002 -- 0001 -- CSR125 MAC Enhanced Configuration Control (DEFAULT = 603c) bits [15:8] = IPG, InterPacket Gap (Default = 60xx, 96 bit times) bits [8:0] = IFS1, InterFrame Space Part 1 (Default = xx3c, 60 bit times) |
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