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AM79C978VC/W 数据表(PDF) 47 Page - Advanced Micro Devices

部件名 AM79C978VC/W
功能描述  Single-Chip 1/10 Mbps PCI Home Networking Controller
PDF  261 Pages
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制造商  AMD [Advanced Micro Devices]
网页  http://www.amd.com
标志 AMD - Advanced Micro Devices

AM79C978VC/W 数据表(HTML) 47 Page - Advanced Micro Devices

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Am79C978
47
Figure 18.
Disconnect With Data Transfer
Disconnect Without Data Transfer
Figure 19 shows a target disconnect sequence during
which no data is transferred. STOP is asserted on clock
4 without TRDY being asserted at the same time. The
Am79C978 controller terminates the access with the
deassertion of FRAME on clock 5 and of IRDY one
clock cycle later. It finally releases the bus on clock 7.
The Am79C978 controller will again request the bus
after two clock cycles to retry the last transfer. The
starting address of the new transfer will be the address
of the last non-transferred data.
Target Abort
Figure 20 shows a target abort sequence. The target
asserts DEVSEL for one clock. It then deasserts
DEVSEL and asserts STOP on clock 4. A target can
use the target abort sequence to indicate that it can-
not service the data transfer and that it does not want
the tran saction to be retrie d. Additionally, the
Am79C978 controller cannot make any assumption
about the success of the previous data transfers in the
current transaction. The Am79C978 controller termi-
nates the current transfer with the deassertion of
FRAME on clock 5 and of IRDY one clock cycle later.
It finally releases the bus on clock 6.
Since data integrity is not guaranteed, the Am79C978
controller cannot recover from a target abort event.
TheAm79C978 controller will reset all CSR locations to
their STOP_RESET values. The BCR and PCI config-
uration registers will not be cleared. Any on-going net-
wo rk tran smission is te rm inated in an orde rly
sequence. If less than 512 bits have been transmitted
onto the network, the transmission will be terminated
immediately, generating a runt packet. If 512 bits or
more have been transmitted, the message will have the
current FCS inverted and appended at the next byte
boundary to guarantee an FCS error is detected at the
receiving station.
FRAME
CLK
AD
IRDY
TRDY
C/BE
DEVSEL
REQ
GNT
PAR
DEVSEL
is sampled
ADDRi
0000
0111
PAR
0111
2
3456789
11
10
PAR
DATA
STOP
ADDRi+8
DATA
1
22206B-21



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