AM79C978VCSLASHW datasheet(92/261 Pages) AMD

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Am79C978

NAND Tree Testing

The controller provides a NAND tree test mode to allow

checking connectivity to the device on a printed circuit

board. The NAND tree is built on all PCI bus pins.

NAND tree testing is enabled by asserting RST. PG

input should be driven HIGH during NAND tree testing.

All PCI bus signals will become inputs on the assertion

of RST. The result of the NAND tree test can be ob-

served on the INTA pin. See Figure 48.

Pin 141 (RST) is the first input to the NAND tree. Pin

142 (CLK) is the second input to the NAND tree, fol-

lowed by pin 143 (GNT). All other PCI bus signals fol-

low, counterclockwise, with pin 61 (AD0) being the last.

Table 21 and Table 22 shows the complete list of pins

connected to the NAND tree.

RST must be asserted low to start a NAND tree test se-

quence. Initially, all NAND tree inputs except RST

should be driven high. This will result in a high output

at the INTA pin. If the NAND tree inputs are driven from

high to low in the same order as they are connected to

build the NAND tree, INTA will toggle every time an ad-

ditional input is driven low. INTA will change to low,

when CLK is driven low and all other NAND tree inputs

stay high. INTA will toggle back to high, when GNT is

additionally driven low. The square wave will continue

until all NAND tree inputs are driven low. INTA will be

high, when all NAND tree inputs are driven low. See

Figure 49.

Some of the pins connected to the NAND tree are out-

puts in normal mode of operation. They must not be

driven from an external source until the controller is

configured for NAND tree testing.

Figure 48.

NAND Tree Circuitry (160 PQFP)

Am79C972

Core

RST (pin141)

CLK (pin 142)

VDD

GNT (pin 143)

AD0 (pin 61)

INTA (pin 140)

MUX

....

INTA

Am79C978

Core

22206B-52

AM79C978VC/W 数据表(PDF) 92 Page - Advanced Micro Devices

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