AM79C978VCSLASHW datasheet(46/261 Pages) AMD

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Am79C978

ample, the memory system extends the data phase of

the first access by one wait state. The following three

data phases take one clock cycle each, which is deter-

mined by the timing of TRDY. The example assumes

that EXTREQ (BCR18, bit 8) is set to 1, therefore, REQ

is not deasserted until the next to last data phase is fin-

ished.

Target Initiated Termination

When the Am79C978 controller is a bus master, the cy-

cles it produces on the PCI bus may be terminated by

the target in one of three different ways: disconnect

with data transfer, disconnect without data transfer, and

target abort.

Disconnect With Data Transfer

Figure 18 shows a disconnection in which one last data

transfer occurs after the target asserted STOP. STOP

is asserted on clock 4 to start the termination se-

quence. Data is still transferred during this cycle, since

both IRDY and TRDY are asserted. The Am79C978

controller terminates the current transfer with the deas-

sertion of FRAME on clock 5 and of IRDY one clock

later. It finally releases the bus on clock 7. If it wants to

transfer more data, the Am79C978 controller will again

request the bus after two clock cycles. The starting ad-

dress of the new transfer will be the address of the next

non-transferred data.

Figure 17.

Burst Write Transfer (EXTREQ = 1)

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

REQ

GNT

2345678

ADDR

DATA

0111

PAR

DATA

PAR

DEVSEL

is sampled

22206B-20

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