AM79C978VCSLASHW datasheet(74/261 Pages) AMD

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Am79C978

When operating in full-duplex mode, the following

changes to the device operation are made:

Bus Interface/Buffer Management Unit changes:

n The first 64 bytes of every transmit frame are not

preserved in the Transmit FIFO during transmission

of the first 512 bits as described in the Transmit Ex-

ception Conditions section. Instead, when full-du-

plex mode is active and a frame is being transmitted,

the XMTFW bits (CSR80, bits 9-8) always govern

when transmit DMA is requested.

n Successful reception of the first 64 bytes of every

receive frame is not a requirement for Receive DMA

to begin as described in the Receive Exception Con-

ditions section. Instead, receive DMA will be re-

quested as soon as either the RCVFW threshold

(CSR80, bits 12-13) is reached or a complete valid

receive frame is detected, regardless of length. This

Receive FIFO operation is identical to when the RPA

bit (CSR124, bit 3) is set during half-duplex mode

operation.

The MAC engine changes for full-duplex operation are

as follows:

n Changes to the transmit deferral mechanism:

— Transmission is not deferred while receive is

active.

— The IPG counter which governs transmit deferral

during the IPG between back-to-back transmits

is started when transmit activity for the first

packet ends, instead of when transmit and car-

rier activity ends.

n The 4.0 µs carrier sense blinding period after a

transmission during which the SQE test normally

occurs is disabled.

n The collision indication input to the MAC engine is

ignored.

The internal PHY changes for full-duplex operation are

as follows:

n The collision detect (COL) pin is disabled.

n The SQE test function is disabled.

n Loss of Carrier (LCAR) reporting is disabled.

n PHY Control Register (TBR0) bit 8 is set to 1 if Auto-

Negotiation is disabled.

Full-Duplex Link Status LED Support

TheAm79C978 controller provides bits in each of the

LED Status registers (BCR4, BCR5, BCR6, BCR7, and

BCR48) to display the Full-Duplex Link Status. If the

FDLSE bit (bit 8) is set, a value of 1 will be sent to the

associated LEDOUT bit when in Full-Duplex.

PHY/MAC Interface

The internal MII-compatible interface provides the data

path connection between the 10BASE-T PHY, the 1

Mbps HomePNA PHY, and the 10/100 Media Access

Controller (MAC). The interface is compatible with

Clause 22 of the IEEE 802.3 standard specification.

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