AM79C978VCSLASHW datasheet(31/261 Pages) AMD

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Am79C978

TX_EN

Transmit Enable

Output

TX_EN indicates when the Am79C978 device is pre-

senting valid transmit nibbles on the MII TXD[3:0] bus.

While TX_EN is asserted, the Am79C978 device gen-

erates TXD[3:0] and TX_ER on TX_CLK rising edges.

TX_EN is asserted with the first nibble of preamble and

remains asserted throughout the duration of the packet

until it is deasserted prior to the first TX_CLK following

the final nibble of the frame. TX_EN transitions are syn-

chronous to TX_CLK.

MDC

Management Data Clock

Output

MDC is the non-continuous clock output that provides

a timing reference for bits on the MDIO pin. During MII

management port operations, MDC runs at a nominal

frequency of 2.5 MHz. When no management opera-

tions are in progress, MDC is driven LOW.

If the MII port is not selected, the MDC pin may be left

floating.

MDIO

Management Data Input/Output

Input/

Output

MDIO is a bidirectional MII management port data pin.

MDIO is an output during the header portion of the

management frame transfers and during the data por-

tion of write operations. MDIO is an input during the

data portion of read operations.

If a PHY is attached to the MII port via a MII physical

connector then the MDIO pin should be externally

pulled down to Vss with a 10 k

Ω ±5% resistor. If a PHY

is directly attached to the MII pins then the MDIO pin

should be externally pulled up to Vcc with a 10 k

Ω ±5%

resistor.

IEEE 1149.1 (1990) Test Access Port

Interface

TCK

Test Clock

Input

TCK is the clock input for the boundary scan test mode

operation. It can operate at a frequency of up to 10

MHz. TCK has an internal pull-up resistor.

TDI

Test Data In

Input

TDI is the test data input path to the Am79C978 con-

troller. The pin has an internal pull-up resistor.

TDO

Test Data Out

Output

TDO is the test data output path from the Am79C978

controller. The pin is tri-stated when the JTAG port is in-

active.

TMS

Test Mode Select

Input

A serial input bit stream on the TMS pin is used to de-

fine the specific boundary scan test to be executed.

The pin has an internal pull-up resistor.

Ethernet Network Interfaces

TX±

Serial Transmit Data

Output

These pins carry the transmit output data and are con-

nected to the transmit side of the magnetics module.

RX±

Serial Receive Data

Input

These pins accept the receive input data from the mag-

netics module.

IREF

Internal Current Reference

Input

This pin serves as a current reference for the inte-

grated 1/10 PHY. It must be connected to VSS through

a 12100-

Ω resistor (1%).

PHY_RST

PHY Reset

Output

This output is used to reset the external PHY. This out-

put eliminates the need for a fanout buffer on the PCI

reset (RST) signal, provided polarity control for the

specific PHY used, and prevents the resetting of the

PHY when the PG input is LOW. The output polarity is

determined by the RST_POL (CRS116, bit0).

HomePNA PHY Network Interface

HRTXRXP/HRTXRXN

Serial Receive Data

Input/Output

These pins accept the receive input data from the mag-

netics module and carry the transmit output data. A

102-

Ω resistor should be placed between these pins.

Clock Interface

XCLK/XTAL

External Clock/Crystal Select

Input

When HIGH, an external 60-MHz clock source is se-

lected bypassing the crystal circuit and clock trippler.

When LOW, a 20-MHz crystal is used instead. The fol-

lowing table illustrates how this pin works.

AM79C978VC/W 数据表(PDF) 31 Page - Advanced Micro Devices

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AM79C978VC/W 数据表(PDF) 31 Page - Advanced Micro Devices

AM79C978VC/W 数据表(HTML) 31 Page - Advanced Micro Devices

Html Pages

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