AM79C978VCSLASHW datasheet(40/261 Pages) AMD

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Am79C978

Disconnect When Busy

The Am79C978 controller cannot service any slave ac-

cess while it is reading the contents of the EEPROM.

Simultaneous access is not allowed in order to avoid

conflicts, since the EEPROM is used to initialize some

of the PCI configuration space locations and most of

the BCRs and CSR116. The EEPROM read operation

will always happen automatically after the deassertion

of the RST pin. In addition, the host can start the read

operation by setting the PREAD bit (BCR19, bit 14).

While the EEPROM read is on-going, the Am79C978

controller will disconnect any slave access where it is

the target by asserting STOP together with DEVSEL,

while driving TRDY high. STOP will stay asserted until

the end of the cycle.

A second situation where the Am79C978 controller will

generate a PCI disconnect/retry cycle is when the host

tries to access any of the I/O resources right after hav-

ing read the Reset register. Since the access gener-

ates an internal reset pulse of about 1 ms in length, all

further slave accesses will be deferred until the internal

reset operation is completed. See Figure 8.

Disconnect Of Burst Transfer

The Am79C978 controller does not support burst ac-

cess to the configuration space, the I/O resources, or

to the Expansion Bus. The host indicates a burst trans-

action by keeping FRAME asserted during the data

phase. When the Am79C978 controller sees FRAME

and IRDY asserted in the clock cycle before it wants to

assert TRDY, it also asserts STOP at the same time.

The transfer of the first data phase is still successful,

since IRDY and TRDY are both asserted. See Figure 9.

If the host is not yet ready when the Am79C978 control-

ler asserts TRDY, the device will wait for the host to as-

sert IRDY. When the host asserts IRDY and FRAME is

still asserted, the Am79C978 controller will finish the

first data phase by deasserting TRDY one clock later.

At the same time, it will assert STOP to signal a discon-

nect to the host. STOP will stay asserted until the host

removes FRAME. See Figure 10.

Figure 8.

Disconnect of Slave Cycle When Busy

Figure 9.

Disconnect of Slave Burst Transfer - No

Host Wait States

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

2345

CMD

PAR

DATA

ADDR

22206B-11

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

STOP

2345

PAR

DATA

1st DATA

22206B-12

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