AM79C978VCSLASHW datasheet(28/261 Pages) AMD

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Am79C978

When RST is active, REQ is an input for NAND tree

testing.

RST

Reset

Input

When RST is asserted LOW and the PG pin is HIGH,

then the Am79C978 controller performs an internal

syste m

r e set

the

t y pe

H _ R ESET

(HARDWARE_RESET, see section on RESET). RST

must be held for a minimum of 30 clock periods. While

in the H_RESET state, the Am79C978 controller will

disable or deassert all outputs. RST may be asynchro-

nous to clock when asserted or deasserted.

When the PG pin is LOW, RST disables all of the PCI

pins except the PME pin.

When RST is LOW and PG is HIGH, NAND tree testing

is enabled.

SERR

System Error

Output

During any slave transaction, the Am79C978 controller

asserts SERR when it detects an address parity error,

and reporting of the error is enabled by setting PER-

REN (PCI Command register, bit 6) and SERREN (PCI

Command register, bit 8) to 1.

By default SERR is an open-drain output. For compo-

nent test, it can be programmed to be an active-high

totem-pole output.

When RST is active, SERR is an input for NAND tree

testing.

STOP

Stop

Input/Output

In slave mode, the Am79C978 controller drives the

STOP signal to inform the bus master to stop the cur-

rent transaction. In bus master mode, the Am79C978

controller checks STOP to determine if the target wants

to disconnect the current transaction.

When RST is active, STOP is an input for NAND tree

testing.

TRDY

Target Ready

Input/Output

TRDY indicates the ability of the target of the transac-

tion to complete the current data phase. Wait states are

inserted until both IRDY and TRDY are asserted simul-

taneously. A data phase is completed on any clock

when both IRDY and TRDY are asserted.

When the Am79C978 controller is a bus master, it

checks TRDY during all read data phases to determine

if valid data is present on AD[31:0]. During all write data

phases, the device checks TRDY to determine if the

target is ready to accept the data.

When the Am79C978 controller is the target of a trans-

action, it asserts TRDY during all read data phases to

indicate that valid data is present on AD[31:0]. During

all write data phases, the device asserts TRDY to indi-

cate that it is ready to accept the data.

When RST is active, TRDY is an input for NAND tree

testing.

Magic Packet Interface

PME

Power Management Event

Output, Open Drain

PME is an output that can be used to indicate that a

power management event (a Magic Packet, an OnNow

pattern match, or a change in link state) has been de-

tected. The PME pin is asserted when either

1. PME_STATUS and PME_EN are both 1,

2. PME_EN_OVR and MPMAT are both 1, or

3. PME_EN_OVR and LCDET are both 1.

The PME signal is asynchronous with respect to the

PCI clock. See the Power Saving Mode section for de-

tailed description.

Power Good

Input

The PG pin has two functions: (1) it puts the device into

Magic Packet mode, and (2) it blocks any resets when

the PCI bus power is off.

When PG is LOW and either MPPEN or MPMODE is

set to 1, the device enters Magic Packet mode.

When PG is LOW, a LOW assertion of the PCI RST pin

will only cause the PCI interface pins (except for PME)

to be put in the high impedance state. The internal logic

will ignore the assertion of RST.

When PG is HIGH, assertion of the PCI RST pin

causes the controller logic to be reset and the configu-

ration information to be loaded from the EEPROM.

Note: PG input should be kept high during NAND tree

testing.

Board Interface

Note: Before programming the LED pins, see the

description of LEDPE in BCR2, bit 12.

LED0

Output

This output is designed to directly drive an LED. By de-

fault, LED0 indicates an active link connection. This pin

can also be programmed to indicate other network sta-

tus (see BCR4). The LED0 pin polarity is programma-

ble, but by default it is active LOW. When the LED0 pin

polarity is programmed to active LOW, the output is an

open drain driver. When the LED0 pin polarity is pro-

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