AM79C978VCSLASHW datasheet(63/261 Pages) AMD

63 / 261 page

Am79C978

1. The controller does not own the current TDTE and

TXDPOLL = 0 (CSR4, bit 12) and TXON = 1 (CSR0,

bit 4) and the poll time has elapsed, or

2. The controller does not own the current TDTE and

TXDPOLL = 0 and TXON = 1 and a frame has just

been received, or

3. The controller does not own the current TDTE and

TXDPOLL = 0 and TXON = 1 and a frame has just

been transmitted.

Setting the TDMD bit of CSR0 will cause the microcode

controller to exit the poll counting code and immedi-

ately perform a polling operation. If RDTE ownership

has not been previously established, then an RDTE

poll will be performed ahead of the TDTE poll. If the mi-

crocode is not executing the poll counting code when

the TDMD bit is set, then the demanded poll of the

TDTE will be delayed until the microcode returns to the

poll counting code.

The user may change the poll time value from the de-

fault of 65,536 clock periods by modifying the value in

the Polling Interval register (CSR47).

Transmit Descriptor Table Entry

If, after a Transmit Descriptor Table Entry (TDTE) ac-

cess, the Am79C978 controller finds that the OWN bit

of that TDTE is not set, the Am79C978 controller re-

sumes the poll time count and re-examines the same

TDTE at the next expiration of the poll time count.

If the OWN bit of the TDTE is set, but the Start of

Packet (STP) bit is not set, the Am79C978 controller

will immediately request the bus in order to clear the

OWN bit of this descriptor. (This condition would nor-

mally be found following a late collision (LCOL) or retry

(RTRY) error that occurred in the middle of a transmit

frame chain of buffers.) After resetting the OWN bit of

this descriptor, the Am79C978 controller will again im-

mediately request the bus in order to access the next

TDTE location in the ring.

If the OWN bit is set and the buffer length is 0, the OWN

bit will be cleared. In the C-LANCE device, the buffer

length of 0 is interpreted as a 4096-byte buffer. A zero

length buffer is acceptable as long as it is not the last

buffer in a chain (STP = 0 and ENP = 1).

If the OWN bit and STP are set, then microcode control

proceeds to a routine that will enable transmit data

transfers to the FIFO. TheAm79C978 controller will

look ahead to the next transmit descriptor after it has

performed at least one transmit data transfer from the

first buffer.

If the Am79C978 controller does not own the next

TDTE (i.e., the second TDTE for this frame), it will com-

plete transmission of the current buffer and update the

status of the current (first) TDTE with the BUFF and

UFLO bits being set. If DXSUFLO (CSR3, bit 6) is

cleared to 0, the underflow error will cause the trans-

mitter to be disabled (CSR0,

TXON = 0).

TheAm79C978 controller will have to be re-initialized to

restore the transmit function. Setting DXSUFLO to 1

enables the Am79C978 controller to gracefully recover

from an underflow error. The device will scan the trans-

mit descriptor ring until it finds either the start of a new

frame or a TDTE it does not own. To avoid an underflow

situation in a chained buffer transmission, the system

should always set the transmit chain descriptor own

bits in reverse order.

If the Am79C978 controller does own the second TDTE

in a chain, it will gradually empty the contents of the first

buffer (as the bytes are needed by the transmit opera-

tion), perform a single-cycle DMA transfer to update

the status of the first descriptor (clear the OWN bit in

TMD1), and then it may perform one data DMA access

on the second buffer in the chain before executing an-

other lookahead operation. (i.e., a

lookahead to the

third descriptor.)

It is imperative that the host system never reads the

TDTE OWN bits out of order. TheAm79C978 controller

normally clears OWN bits in strict FIFO order. How-

ever, the Am79C978 controller can queue up to two

frames in the transmit FIFO. When the second frame

uses buffer chaining, the Am79C978 controller might

return ownership out of normal FIFO order. The OWN

bit for the last (and maybe only) buffer of the first frame

is not cleared until transmission is completed. During

the transmission the Am79C978 controller will read in

buffers for the next frame and clear their OWN bits for

all but the last one. The first and all intermediate buffers

of the second frame can have their OWN bits cleared

before the Am79C978 controller returns ownership for

the last buffer of the first frame.

If an error occurs in the transmission before all of the

bytes of the current buffer have been transferred,

transmit status of the current buffer will be immediately

updated. If the buffer does not contain the end of

packet, the Am79C978 controller will skip over the rest

of the frame which experienced the error. This is done

by returning to the polling microcode where the

Am79C978 controller will clear the OWN bit for all de-

scriptors with OWN = 1 and STP = 0 and continue in

like manner until a descriptor with OWN = 0 (no more

transmit frames in the ring) or OWN = 1 and STP = 1

(the first buffer of a new frame) is reached.

At the end of any transmit operation, whether success-

ful or with errors, immediately following the completion

of the descriptor updates, the Am79C978 controller will

always perform another polling operation. As described

earlier, this polling operation will begin with a check of

the current RDTE, unless the Am79C978 controller al-

ready owns that descriptor. Then the Am79C978 con-

troller will poll the next TDTE. If the transmit descriptor

OWN bit has a 0 value, the Am79C978 controller will

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