AM79C978VCSLASHW datasheet(84/261 Pages) AMD

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Am79C978

EEPROM Interface

The controller contains a built-in capability for reading

and writing to an external serial 93C46 EEPROM. This

built-in capability consists of an interface for direct con-

nection to a 93C46 compatible EEPROM, an automatic

EEPROM read feature, and a user-programmable reg-

ister that allows direct access to the interface pins.

Automatic EEPROM Read Operation

Shortly after the deassertion of the RST pin, the con-

troller will read the contents of the EEPROM that is at-

tached to the interface. Because of this automatic-read

capability of the controller, an EEPROM can be used to

program many of the features of the controller at

power-up, allowing system-dependent configuration in-

formation to be stored in the hardware instead of inside

the device driver.

If an EEPROM exists on the interface, the controller will

read th e EEPROM contents at the end of the

H_RESET operation. The EEPROM contents will be

serially shifted into a temporary register and then sent

to various register locations on board the controller. Ac-

cess to the Am79C978 configuration space or any I/O

resource is not possible during the EEPROM read op-

eration. The controller will terminate any access at-

tempt with the assertion of DEVSEL and STOP while

TRDY is not asserted, signaling to the initiator to dis-

connect and retry the access at a later time.

A checksum verification is performed on the data that

is read from the EEPROM. If the checksum verification

passes, PVALID (BCR19, bit 15) will be set to 1. If the

checksum verification of the EEPROM data fails,

PVALID will be cleared to 0, and the controller will force

all EEPROM-programmable BCR registers back to

their H_RESET default values. However, the content of

the Address PROM locations (offsets 0h - Fh from the

I/O or memory mapped I/O base address) will not be

cleared. The 8-bit checksum for the entire 82 bytes of

the EEPROM should be FFh.

If no EEPROM is present at the time of the automatic

read operation, the controller will recognize this condi-

tion, abort the automatic read operation, and clear both

the PREAD and PVALID bits in BCR19. All EEPROM-

programmable BCR registers will be assigned their de-

fault values after H_RESET. The content of the Ad-

dress PROM locations (offsets 0h - Fh from the I/O or

memory mapped I/O base address) will be undefined.

EEPROM Auto-Detection

The controller uses the EESK/LED1 pin to determine if

an EEPROM is present in the system. At the rising

edge of CLK during the last clock during which RST is

asserted, the controller will sample the value of the

EESK/LED1 pin. If the sampled value is a 1, then the

controller assumes that an EEPROM is present, and

the EEPROM read operation begins shortly after the

RST pin is deasserted. If the sampled value of EESK/

LED1 is a 0, the controller assumes that an external

pull-down device is holding the EESK/LED1 pin low, in-

dicating that there is no EEPROM in the system. Note

that if the designer creates a system that contains an

LED circuit on the EESK/LED1 pin, but has no EE-

PROM present, then the EEPROM auto-detection

function will incorrectly conclude that an EEPROM is

present in the system. However, this will not pose a

problem for the controller, since the checksum verifica-

tion will fail.

Direct Access to the Interface

The user may directly access the port through the

EEPROM register, BCR19. This register contains bits

that can be used to control the interface pins. By per-

forming an appropriate sequence of accesses to

BCR19, the user can effectively write to and read from

the EEPROM. This feature may be used by a system

configuration utility to program hardware configuration

information into the EEPROM.

EEPROM-Programmable Registers

The following registers contain configuration informa-

tion that will be programmed automatically during the

EEPROM read operation:

n I/O offsets 0h-Fh Address PROM locations

n BCR2

Miscellaneous Configuration

n BCR4

LED0 Status

n BCR5

LED1 Status

n BCR6

LED2 Status

n BCR7

LED3 Status

n BCR9

Full-Duplex Control

n BCR18

Burst and Bus Control

n BCR22

PCI Latency

n BCR23

PCI Subsystem Vendor ID

n BCR24

PCI Subsystem ID

n BCR25

SRAM Size

n BCR26

SRAM Boundary

n BCR27

SRAM Interface Control

n BCR32

PHY Control and Status

n BCR33

PHY Address

n BCR35

PCI Vendor ID

n BCR36

PCI Power Management Capa-

bilities (PMC) Alias Register

n BCR37

PCI DATA Register 0 (DATA0)

Alias Register

n BCR38

PCI DATA Register 1 (DATA1)

Alias Register

n BCR39

PCI DATA Register 2 (DATA2)

Alias Register

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