AM79C978VCSLASHW datasheet(98/261 Pages) AMD

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Am79C978

Table 27.

I/O Map in DWord I/O Mode (DWIO = 1)

Table 28.

Legal I/O Accesses in Double Word I/O

Mode (DWIO =1)

10BASE-T Physical Layer

The 10BASE-T block consists of the following sub-

blocks:

— Transmit Process

— Receive Process

— Interface Status

— Collision Detect Function

— Jabber Function

— Reverse Polarity Detect

Refer to Figure 50 for the 10BASE-T block diagram.

Twisted Pair Transmit Function

Data transmission over the 10BASE-T medium re-

quires use of the integrated 10BASE-T MAU and uses

the differential driver circuitry on the TX± pins.

TX± is a differential twisted-pair driver. When properly

terminated, TX± will meet the transmitter electrical re-

quirements for 10BASE-T transmitters as specified in

IEEE 802.3, Section 14.3.1.2. The load is a twisted pair

cable that meets IEEE 802.3, Section 14.4.

The TX± signal is filtered on the chip to reduce har-

monic content per Section 14.3.2.1 (10BASE-T). Since

filtering is performed in silicon, TX± can be connected

directly to a standard transformer. External filtering

modules are not needed.

Twisted Pair Receive Function

The RX+ port is a differential twisted-pair receiver.

When properly terminated, the RX+ port will meet the

electrical requirements for 10BASE-T receivers as

specified in IEEE 802.3, Section 14.3.1.3. The receiver

has internal filtering and does not require external filter

modules or common mode chokes.

Signals appearing at the RX± differential input pair are

routed to the internal decoder. The receiver function

meets the propagation delays and jitter requirements

specified by the 10BASE-T standard. The receiver

squelch level drops to half its threshold value after un-

squelch to allow reception of minimum amplitude sig-

nals and to mitigate carrier fade in the event of worst

case signal attenuation and crosstalk noise conditions.

Figure 50.

10BASE-T Transmit and Receive Data

Paths

Twisted Pair Interface Status

The Am79C978 device will power up in the Link Fail

state. The Auto-Negotiation algorithm will apply to

allow it to enter the Link Pass state.

Offset

No. of Bytes

00h - 0Fh

APROM

10h

RDP

14h

RAP (shared by RDP and

BDP)

18h

Reset Register

1Ch

BDP

AD[4:0]

BE[3:0]

Type

Comment

0XX00

0000

DWord read of APROM

locations 3h (MSB) to 0h

(LSB),

7h to 4h, Bh to 8h, or Fh to

10000

0000

DWord read of RDP

10100

0000

DWord read of RAP

11000

0000

DWord read of Reset

0XX00

0000

DWord write to APROM

locations 3h (MSB) to 0h

(LSB),

7h to 4h, Bh to 8h, or Fh to

10000

0000

DWord write to RDP

10100

0000

DWord write to RAP

11000

0000

DWord write to Reset

Clock

Data

Manchester

Encoder

Clock

Data

Manchester

Decoder

Squelch

Circuit

RX Driver

RX±

TX±

TX Driver

22206B-54

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