AM79C978VCSLASHW datasheet(67/261 Pages) AMD

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Am79C978

Media Access Management

The basic requirement for all stations on the network is

to provide fairness of channel allocation. The IEEE

802.3/Ethernet protocols define a media access mech-

anism which permits all stations to access the channel

with equality. Any node can attempt to contend for the

channel by waiting for a predetermined time (Inter

Packet Gap) after the last activity, before transmitting

on the media. The channel is a multidrop communica-

tions media (with various topological configurations

permitted), which allows a single station to transmit and

all other stations to receive. If two nodes simulta-

neously contend for the channel, their signals will inter-

act causing loss of data, defined as a collision. It is the

responsibility of the MAC to attempt to avoid and

recover from a collision and to guarantee data integrity

for the end-to-end transmission to the receiving station.

Medium Allocation

The IEEE/ANSI 802.3 standard (ISO/IEC 8802-3 1990)

requires that the CSMA/CD MAC monitor the medium

for traffic by watching for carrier activity. When carrier

is detected, the media is considered busy, and the

MAC should defer to the existing message.

The ISO 8802-3 (IEEE/ANSI 802.3) standard also

allows optionally a two-part deferral after a receive

message.

See ANSI/IEEE Std 802.3-1993 Edition, 4.2.3.2.1:

Note: “It is possible for the PLS carrier sense indica-

tion to fail to be asserted during a collision on the me-

dia. If the deference process simply times the inter-

frame gap based on this indication, it is possible for a

short interframe gap to be generated, leading to a po-

tential reception failure of a subsequent frame. To en-

hance system robustness, the following optional

measures (as specified in 4.2.8) are recommended

when InterFrameSpacingPart1 is other than 0:

1. Upon completing a transmission, start timing the in-

terrupted gap as soon as transmitting and carrier

sense are both false.

2. When timing an inter-frame gap following reception,

reset the inter-frame gap timing if carrier sense be-

comes true during the first 2/3 of the inter-frame gap

timing interval. During the final 1/3 of the interval,

the timer shall not be reset to ensure fair access to

the medium. An initial period shorter than 2/3 of the

interval is permissible including 0.”

The MAC engine implements the optional receive two-

part deferral algorithm, with an InterFrameSpacing-

Part1 time of 6.0 ms. The InterFrameSpacingPart 2 in-

terval is, therefore, 3.4 ms.

TheAm79C978 controller will perform the two-part de-

ferral algorithm as specified in the Process Deference

section. The Inter Packet Gap (IPG) timer will start tim-

ing the 9.6 ms InterFrameSpacing after the receive car-

rier is deasserted. During the first part deferral

(InterFrameSpacingPart1 - IFS1), the Am79C978 con-

troller will defer any pending transmit frame and re-

spond to the receive message. The IPG counter will be

cleared to 0 continuously until the carrier deasserts, at

which point the IPG counter will resume the 9.6 ms

count once again. Once the IFS1 period of 6.0 ms has

elapsed, the Am79C978 controller will begin timing the

second part deferral (InterFrameSpacingPart2 - IFS2)

of 3.4 ms. Once IFS1 has completed and IFS2 has

commenced, the Am79C978 controller will not defer to

a receive frame if a transmit frame is pending. This

means that the Am79C978 controller will not attempt to

receive the receive frame, since it will start to transmit

and generate a collision at 9.6 ms. TheAm79C978 con-

troller will complete the preamble (64-bit) and jam (32-

bit) sequence before ceasing transmission and invok-

ing the random backoff algorithm.

TheAm79C978 controller allows the user to program

t he

I P G

and

the

fir s t - p a r t

d e fe r r a l

(InterFrameSpacingPart1 - IFS1) through CSR125. By

changing the IPG default value of 96 bit times (60h),

the user can adjust the fairness or aggressiveness of

the MAC on the network. By programming a lower

number of bit times than the ISO/IEC 8802-3 standard

requires, the MAC engine will become more aggres-

sive on the network. This aggressive nature will give

rise to the Am79C978 controller possibly capturing the

network at times by forcing other less aggressive com-

pliant nodes to defer. By programming a larger number

of bit times, the MAC will become less aggressive on

the network and may defer more often than normal.

The performance of the Am79C978 controller may de-

crease as the IPG value is increased from the default

value, but the resulting behavior may improve network

performance by reducing collisions. TheAm79C978

controller uses the same IPG for back-to-back trans-

mits and receive-to-transmit accesses. Changing IFS1

will alter the period for which the MAC engine will defer

to incoming receive frames.

CAUTION: Care must be exercised when altering

these parameters. Adverse network activity could

result!

This transmit two-part deferral algorithm is imple-

mented as an option which can be disabled using the

DXMT2PD bit in CSR3. The IFS1 programming will

have no effect when DXMT2PD is set to 1, but the IPG

programming value is still valid. Two part deferral after

transmission is useful for ensuring that severe IPG

shrinkage cannot occur in specific circumstances,

causing a transmit message to follow a receive mes-

sage so closely as to make them indistinguishable.

During the time period immediately after a transmission

has been completed, the external transceiver should

generate the SQE Test message within 0.6 to 1.6 ms

after the transmission ceases. During the time period in

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